From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755450Ab2FDBGK (ORCPT ); Sun, 3 Jun 2012 21:06:10 -0400 Received: from mail-lpp01m010-f46.google.com ([209.85.215.46]:51799 "EHLO mail-lpp01m010-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755385Ab2FDBGI convert rfc822-to-8bit (ORCPT ); Sun, 3 Jun 2012 21:06:08 -0400 MIME-Version: 1.0 In-Reply-To: References: <1337754877-19759-1-git-send-email-yinghai@kernel.org> <20120525043651.GA1391@google.com> <20120525193716.GA8817@google.com> <4FC50E09.4000204@zytor.com> <4FC51D79.6010804@zytor.com> <4FC536A5.6020600@zytor.com> From: Bjorn Helgaas Date: Sun, 3 Jun 2012 18:05:46 -0700 Message-ID: Subject: Re: [PATCH 02/11] PCI: Try to allocate mem64 above 4G at first To: Yinghai Lu Cc: "H. Peter Anvin" , David Miller , Tony Luck , Linus Torvalds , Steven Newbury , Andrew Morton , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT X-System-Of-Record: true Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jun 1, 2012 at 4:30 PM, Yinghai Lu wrote: > On Tue, May 29, 2012 at 1:50 PM, H. Peter Anvin wrote: >> >> The bus-side address space should not be more than 32 bits no matter >> what.  As Bjorn indicates, you seem to be mixing up bus and cpu >> addresses all over the place. > > please check update patches that is using converted pci bus address > for boundary checking. What problem does this fix? There's significant risk that this allocation change will make us trip over something, so it must fix something to make it worth considering. Steve's problem doesn't count because that's a "pci=nocrs" case that will always require special handling. A general solution is not possible without a BIOS change (to describe >4GB apertures) or a native host bridge driver (to discover >4GB apertures from the hardware). These patches only make Steve's machine work by accident -- they make us put the video device above 4GB, and we're just lucky that the host bridge claims that region. One possibility is some sort of boot-time option to force a PCI device to a specified address. That would be useful for debugging as well as for Steve's machine.