From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=DKIMWL_WL_MED,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_PASS,URIBL_BLOCKED,USER_IN_DEF_DKIM_WL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53D94C43610 for ; Mon, 26 Nov 2018 14:51:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1412920663 for ; Mon, 26 Nov 2018 14:51:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="OORiYMsI" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1412920663 Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726672AbeK0Bp0 (ORCPT ); Mon, 26 Nov 2018 20:45:26 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:56307 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726513AbeK0BpZ (ORCPT ); Mon, 26 Nov 2018 20:45:25 -0500 Received: by mail-wm1-f68.google.com with SMTP id y139so18455145wmc.5 for ; Mon, 26 Nov 2018 06:51:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=kFMebdd3rVDX4F6Wrh7uYRhO+8QF8tMUU/jfte+pZG4=; b=OORiYMsI47DjN8FRvdpYvwaaDHYcAYetF9/8pgwWigafI284I4oMtPNY5Yb+bfSc7j ZAhNRzdwsWvFhBzzUUAj5yH46W/rGulFcf6r5z/zMGxvQYCEVWa9hDbWlAtxpYCgqVtd UcxbLakWWthfiDkfwP6dkqUa9sM3eD7Yba2wu148qiXxpHy0lT45Cwf8EoxH8PXZkSEt 1tE6RCUaaBwSheHdQ8LVvouNLM6q6xr2voFSjI18GAtA3lgezqgZNWb+pkUi8M9z4vOH mK1ooIcWPy+I71Nmw38yLsMUhAXs1rzF29p2Kz5YF/fpjoCJDEBPgRlBOwYl2sj+HJRb DvJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=kFMebdd3rVDX4F6Wrh7uYRhO+8QF8tMUU/jfte+pZG4=; b=In5ZE7T2oScXRYr+4dIJ17e21FeWD0Uk3k0vbw6yDw05SfsNAFtaPMHwCzIVU+MqTm uxncfb3mFD2Hc9U4qO0Wab5YKhMt4LdfNdv05HSkIhYRano31A17lnQhAEyM28WPQAkE dd2JcPpd0IKrsZyMvBL9gw5Ev5+620F8iZVZ/1Qdjyw5SSg1HZfU9kGrVW5VRx3csSf2 cINxMmBR1skE+NtQPNE3SkMNZxfntMLSWh1A7S3/fKFyoMFxxL0MawItoIYm/X8tzk10 lJhnnB1cITQeklw7p78v3wX12GR06TnHV3Hw/H7AyFaLUk0rEiO1wv2ees8eFgIhV2gE HSuQ== X-Gm-Message-State: AGRZ1gLySGqsjjyfyHquu9b/hfCrB7hKLb3iEQvBSouByV2yyqrCgl1n AU03DHowIQ9vo1uxqo5mwRJTwkGBFoFy4Uy15GyA X-Google-Smtp-Source: AJdET5eLN3Ygw662ck0Gn3zC+eXaxK5/GRvOjNU/JhBJ48nU7m3unMyBNGYwjkQWhXVIdcrggZGPI/imO9bDf66VpPo= X-Received: by 2002:a1c:4046:: with SMTP id n67mr23174655wma.123.1543243862859; Mon, 26 Nov 2018 06:51:02 -0800 (PST) MIME-Version: 1.0 References: <20181123141831.8214-1-miquel.raynal@bootlin.com> In-Reply-To: <20181123141831.8214-1-miquel.raynal@bootlin.com> From: Bjorn Helgaas Date: Mon, 26 Nov 2018 08:50:51 -0600 Message-ID: Subject: Re: [PATCH 00/12] Bring suspend to RAM support to PCIe Aardvark driver To: miquel.raynal@bootlin.com Cc: gregory.clement@bootlin.com, Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , thomas.petazzoni@bootlin.com, devicetree@vger.kernel.org, Rob Herring , Mark Rutland , Lorenzo Pieralisi , linux-pci@vger.kernel.org, Linux Kernel Mailing List , linux-arm , antoine.tenart@bootlin.com, maxime.chevallier@bootlin.com, Nadav Haklai Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Nov 23, 2018 at 8:18 AM Miquel Raynal w= rote: > > Hello, > > As part of an effort to bring suspend to RAM support to Armada 3700 > SoCs (main target: ESPRESSObin), this series handles the work around > the PCIe IP. > > First, more configuration is done in the 'setup' helper as inspired > from the U-Boot driver. This is needed to entirely initialize the IP > during future resume operation (patch 1). > > Then, reset GPIO, PHY and clock support are introduced (patch 2-4). As > current device trees do not provide the corresponding properties, not > finding one of these properties is not an error and just produces a > warning. However, if the property is present, an error during PHY > initialization will fail the probe of the driver. > > Note: To be sure the clock will be resumed before this driver, a first > series adding links between clocks and consumers has been submitted, > see [1]. > > Patch 5 adds suspend/resume hooks, re-using all the above. > > Finally, bindings and device trees are updated to reflect the hardware > (patch 6-12). While the clock depends on the SoC, the reset GPIO and > the PHY depends on the board so the clock is added in the > armada-37xx.dtsi file while the two other properties are added in > armada-3720-espressobin.dts. > > [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-November/6= 14527.html > > Thanks, > Miqu=C3=A8l > > > Miquel Raynal (12): > PCI: aardvark: configure more registers in the configuration helper > PCI: aardvark: add reset GPIO support > PCI: aardvark: add PHY support > PCI: aardvark: add clock support > PCI: aardvark: add suspend to RAM support > dt-bindings: PCI: aardvark: describe the reset-gpios property > dt-bindings: PCI: aardvark: describe the clocks property > dt-bindings: PCI: aardvark: describe the PHY property > ARM64: dts: marvell: armada-37xx: declare PCIe reset pin > ARM64: dts: marvell: armada-3720-espressobin: declare PCIe reset GPIO > ARM64: dts: marvell: armada-37xx: declare PCIe clock > ARM64: dts: marvell: armada-3720-espressobin: declare PCIe PHY Hi Miqu=C3=A8l, Thanks for your work! If/when you post a v2, please run "git log --oneline" and adjust your subject lines to match the capitalization conventions, i.e., for PCI, start the description with a capital letter: "PCI: aardvark: Add suspend to RAM support". BTW, I notice you closed your email with "Miqu=C3=A8l", but the patches contain "Miquel". you *should* be able to use the correctly accented version of your name in the Signed-off-by lines. I have tripped over some tool issues, but if we pay attention, we should be able to get it to work. > .../devicetree/bindings/pci/aardvark-pci.txt | 9 + > .../dts/marvell/armada-3720-espressobin.dts | 4 + > arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 5 + > drivers/pci/controller/pci-aardvark.c | 214 ++++++++++++++++++ > 4 files changed, 232 insertions(+) > > -- > 2.19.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 From: bhelgaas@google.com (Bjorn Helgaas) Date: Mon, 26 Nov 2018 08:50:51 -0600 Subject: [PATCH 00/12] Bring suspend to RAM support to PCIe Aardvark driver In-Reply-To: <20181123141831.8214-1-miquel.raynal@bootlin.com> References: <20181123141831.8214-1-miquel.raynal@bootlin.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, Nov 23, 2018 at 8:18 AM Miquel Raynal wrote: > > Hello, > > As part of an effort to bring suspend to RAM support to Armada 3700 > SoCs (main target: ESPRESSObin), this series handles the work around > the PCIe IP. > > First, more configuration is done in the 'setup' helper as inspired > from the U-Boot driver. This is needed to entirely initialize the IP > during future resume operation (patch 1). > > Then, reset GPIO, PHY and clock support are introduced (patch 2-4). As > current device trees do not provide the corresponding properties, not > finding one of these properties is not an error and just produces a > warning. However, if the property is present, an error during PHY > initialization will fail the probe of the driver. > > Note: To be sure the clock will be resumed before this driver, a first > series adding links between clocks and consumers has been submitted, > see [1]. > > Patch 5 adds suspend/resume hooks, re-using all the above. > > Finally, bindings and device trees are updated to reflect the hardware > (patch 6-12). While the clock depends on the SoC, the reset GPIO and > the PHY depends on the board so the clock is added in the > armada-37xx.dtsi file while the two other properties are added in > armada-3720-espressobin.dts. > > [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-November/614527.html > > Thanks, > Miqu?l > > > Miquel Raynal (12): > PCI: aardvark: configure more registers in the configuration helper > PCI: aardvark: add reset GPIO support > PCI: aardvark: add PHY support > PCI: aardvark: add clock support > PCI: aardvark: add suspend to RAM support > dt-bindings: PCI: aardvark: describe the reset-gpios property > dt-bindings: PCI: aardvark: describe the clocks property > dt-bindings: PCI: aardvark: describe the PHY property > ARM64: dts: marvell: armada-37xx: declare PCIe reset pin > ARM64: dts: marvell: armada-3720-espressobin: declare PCIe reset GPIO > ARM64: dts: marvell: armada-37xx: declare PCIe clock > ARM64: dts: marvell: armada-3720-espressobin: declare PCIe PHY Hi Miqu?l, Thanks for your work! If/when you post a v2, please run "git log --oneline" and adjust your subject lines to match the capitalization conventions, i.e., for PCI, start the description with a capital letter: "PCI: aardvark: Add suspend to RAM support". BTW, I notice you closed your email with "Miqu?l", but the patches contain "Miquel". you *should* be able to use the correctly accented version of your name in the Signed-off-by lines. I have tripped over some tool issues, but if we pay attention, we should be able to get it to work. > .../devicetree/bindings/pci/aardvark-pci.txt | 9 + > .../dts/marvell/armada-3720-espressobin.dts | 4 + > arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 5 + > drivers/pci/controller/pci-aardvark.c | 214 ++++++++++++++++++ > 4 files changed, 232 insertions(+) > > -- > 2.19.1 >