From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.5 required=3.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1730C433DB for ; Fri, 19 Feb 2021 03:22:24 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 888F864D74 for ; Fri, 19 Feb 2021 03:22:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 888F864D74 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C41A66E433; Fri, 19 Feb 2021 03:22:23 +0000 (UTC) Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4384D6E433; Fri, 19 Feb 2021 03:22:22 +0000 (UTC) Received: by mail-ej1-x632.google.com with SMTP id jt13so9547632ejb.0; Thu, 18 Feb 2021 19:22:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=j5kLhKRa64kwf5SXo0g7lrgWVUiYebAqTdPu7c4cx/0=; b=snJvB1vGPFY5FWkZT4BITlggEQXGMWVDvd8Wcx8p5jB5MpiqQflRnJx/8dAbAq0nrw ujyHt8AsBL0ODhj/+hcQDTnajfbk3ifDGKaC3ia38bY0ZES+RlzJHrmfQlA5bD1eHOA8 w0qi1RM/8QbkEWCMB49cW6Vyxu6HgrAp7AwQB48Zh2xb1KuKpZ1zfLJ/L51EMce/7EKd BOpz8LjlE924bKcTLmsdnaR/y4n0rIAHcHgpD0F9RTONVqVm8t7+Q5mzXaQHl+WS878O SGCW6PNX0q71jfTeVtCgqNQG8qw7KD//U7kNwbQkV4j4hIiYRvmlwvpxiOVo6Urg/Kt9 VAWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=j5kLhKRa64kwf5SXo0g7lrgWVUiYebAqTdPu7c4cx/0=; b=qfGU20qVFPhsLD3pwt6zbPgRzpaMe+KGBWYMshcWVn1tNm2kBqaokHz0NL3D7O8VTm cMENBJo7J4kAjRng+2ZaFERsDoGlr5NHgbgJZvoTtiF0B2uD3CaR/JT+agzpSauY0rD5 pZ0dlD9I5FpsjgPiyUjBpptPk6o9TABtvx94UOuPF6kE0iua4DLr3XP4J1Lt0pboP4OF +sgsJmlBMfKb0gg/RN6W+EVhP3PVH/Y0CjrQPSVUkH51U4/ExIFt4+dFZ5NtplGsG+AJ 4mhHR03VpYEUWvv/J7oFVgv2/wkpiritA+4Usow75bLpRibaMYj742qVBZnaNJRCaBjX 8/FA== X-Gm-Message-State: AOAM533uT5v2EGrfzGlgNehmfbgSGuS9qD09Yol/13Netd6/ERnmdXEv VS6g0QTv97yssT6eAepXwNBPREsn79PkbtvQygs= X-Google-Smtp-Source: ABdhPJzgb59/1ii6ZaZVPv4k7Pu4EEGX4rOmmt+tsl4kdOiKJ+EQ2AnE5/EoylxvFhYzqwxxjOSrlDMqn3l1BceleQ0= X-Received: by 2002:a17:906:4013:: with SMTP id v19mr7066311ejj.5.1613704940924; Thu, 18 Feb 2021 19:22:20 -0800 (PST) MIME-Version: 1.0 References: <20210128192413.1715802-1-matthew.d.roper@intel.com> <20210128192413.1715802-19-matthew.d.roper@intel.com> In-Reply-To: From: Mario Kleiner Date: Fri, 19 Feb 2021 04:22:09 +0100 Message-ID: Subject: Re: [Intel-gfx] [PATCH 18/18] drm/i915/display13: Enabling dithering after the CC1 pipe To: =?UTF-8?B?VmlsbGUgU3lyasOkbMOk?= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx , Nischal Varide , dri-devel Content-Type: multipart/mixed; boundary="===============0535643410==" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" --===============0535643410== Content-Type: multipart/alternative; boundary="000000000000c6b07805bba7f5f0" --000000000000c6b07805bba7f5f0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Feb 11, 2021 at 1:29 PM Ville Syrj=C3=A4l=C3=A4 wrote: > On Thu, Jan 28, 2021 at 11:24:13AM -0800, Matt Roper wrote: > > From: Nischal Varide > > > > If the panel is 12bpc then Dithering is not enabled in the Legacy > > dithering block , instead its Enabled after the C1 CC1 pipe post > > color space conversion.For a 6bpc pannel Dithering is enabled in > > Legacy block. > > Dithering is probably going to require a whole uapi bikeshed. > Not sure we can just enable it unilaterally. > > Ccing dri-devel, and Mario who had issues with dithering in the > past... > > Thanks for the cc Ville! The problem with dithering on Intel is that various tested Intel gpu's (Ironlake, IvyBridge, Haswell, Skylake iirc.) are dithering when they shouldn't. If one has a standard 8 bpc framebuffer feeding into a standard (legacy) 256 slots, 8 bit wide lut which was loaded with an identity mapping, feeding into a standard 8 bpc video output (DVI/HDMI/DP), the expected result is that pixels rendered into the framebuffer show up unmodified at the video output. What happens instead is that some dithering is needlessly applied. This is bad for various neuroscience/medical research equipment that requires pixels to pass unmodified in a pure 8 bpc configuration, e.g., because some digital info is color-encoded in-band in the rendered image to control research hardware, a la "if rgb pixel (123, 12, 23) is detected in the digital video stream, emit some trigger signal, or timestamp that moment with a hw clock, or start or stop some scientific recording equipment". Also there exist specialized visual stimulators to drive special displays with more than 12 bpc, e.g., 16 bpc, and so they encode the 8MSB of 16 bpc color values in pixels in even columns, and the 8LSB in the odd columns of the framebuffer. Unexpected dithering makes such equipment completely unusable. By now I must have spent months of my life, just trying to deal with dithering induced problems on different gpu's due to hw quirks or bugs somewhere in the graphics stack. Atm. the intel kms driver disables dithering for anything with >=3D 8 bpc a= s a fix for this harmful hardware quirk. Ideally we'd have uapi that makes dithering controllable per connector (on/off/auto, selectable depth), also in a way that those controls are exposed as RandR output properties, easily controllable by X clients. And some safe default in case the client can't access the properties (like I'd expect to happen with the dozens of Wayland compositors under the sun). Various drivers had this over time, e.g., AMD classic kms path (if i don't misremember) and nouveau, but some of it also got lost in the new atomic kms variants, and Intel never exposed this. Or maybe some method that checks the values actually stored in the hw lut's, CTM etc. and if the values suggest no dithering should be needed, disable the dithering. E.g., if output depth is 8 bpc, one only needs dithering if the slots in the final active hw lut do have any meaningful values in the lower bits below the top 8 MSB, ie. if the content is actually > 8 bpc net bit depth. -mario > > > Cc: Uma Shankar > > Signed-off-by: Nischal Varide > > Signed-off-by: Bhanuprakash Modem > > Signed-off-by: Matt Roper > > --- > > drivers/gpu/drm/i915/display/intel_color.c | 16 ++++++++++++++++ > > drivers/gpu/drm/i915/display/intel_display.c | 9 ++++++++- > > drivers/gpu/drm/i915/i915_reg.h | 3 ++- > > 3 files changed, 26 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c > b/drivers/gpu/drm/i915/display/intel_color.c > > index ff7dcb7088bf..9a0572bbc5db 100644 > > --- a/drivers/gpu/drm/i915/display/intel_color.c > > +++ b/drivers/gpu/drm/i915/display/intel_color.c > > @@ -1604,6 +1604,20 @@ static u32 icl_csc_mode(const struct > intel_crtc_state *crtc_state) > > return csc_mode; > > } > > > > +static u32 dither_after_cc1_12bpc(const struct intel_crtc_state > *crtc_state) > > +{ > > + u32 gamma_mode =3D crtc_state->gamma_mode; > > + struct drm_i915_private *i915 =3D > to_i915(crtc_state->uapi.crtc->dev); > > + > > + if (HAS_DISPLAY13(i915)) { > > + if (!crtc_state->dither_force_disable && > > + (crtc_state->pipe_bpp =3D=3D 36)) > > + gamma_mode |=3D GAMMA_MODE_DITHER_AFTER_CC1; > > + } > > + > > + return gamma_mode; > > +} > > + > > static int icl_color_check(struct intel_crtc_state *crtc_state) > > { > > int ret; > > @@ -1614,6 +1628,8 @@ static int icl_color_check(struct intel_crtc_stat= e > *crtc_state) > > > > crtc_state->gamma_mode =3D icl_gamma_mode(crtc_state); > > > > + crtc_state->gamma_mode =3D dither_after_cc1_12bpc(crtc_state); > > + > > crtc_state->csc_mode =3D icl_csc_mode(crtc_state); > > > > crtc_state->preload_luts =3D intel_can_preload_luts(crtc_state); > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > > index 4dc4b1be0809..e3dbcd956fc6 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -8098,9 +8098,15 @@ static void bdw_set_pipemisc(const struct > intel_crtc_state *crtc_state) > > break; > > } > > > > - if (crtc_state->dither) > > + /* > > + * If 12bpc panel then, Enables dithering after the CC1 pipe > > + * post color space conversion and not here > > + */ > > + > > + if (crtc_state->dither && (crtc_state->pipe_bpp !=3D 36)) > > val |=3D PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP= ; > > > > + > > if (crtc_state->output_format =3D=3D INTEL_OUTPUT_FORMAT_YCBCR420= || > > crtc_state->output_format =3D=3D INTEL_OUTPUT_FORMAT_YCBCR444= ) > > val |=3D PIPEMISC_OUTPUT_COLORSPACE_YUV; > > @@ -10760,6 +10766,7 @@ intel_modeset_pipe_config(struct > intel_atomic_state *state, > > */ > > pipe_config->dither =3D (pipe_config->pipe_bpp =3D=3D 6*3) && > > !pipe_config->dither_force_disable; > > + > > drm_dbg_kms(&i915->drm, > > "hw max bpp: %i, pipe bpp: %i, dithering: %i\n", > > base_bpp, pipe_config->pipe_bpp, pipe_config->dither)= ; > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h > > index 128b835c0adb..27f25214a839 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -6132,7 +6132,7 @@ enum { > > #define PIPEMISC_DITHER_8_BPC (0 << 5) > > #define PIPEMISC_DITHER_10_BPC (1 << 5) > > #define PIPEMISC_DITHER_6_BPC (2 << 5) > > -#define PIPEMISC_DITHER_12_BPC (3 << 5) > > +#define PIPEMISC_DITHER_12_BPC (4 << 5) > > #define PIPEMISC_DITHER_ENABLE (1 << 4) > > #define PIPEMISC_DITHER_TYPE_MASK (3 << 2) > > #define PIPEMISC_DITHER_TYPE_SP (0 << 2) > > @@ -7668,6 +7668,7 @@ enum { > > #define GAMMA_MODE_MODE_12BIT (2 << 0) > > #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */ > > #define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + > */ > > +#define GAMMA_MODE_DITHER_AFTER_CC1 (1 << 26) > > > > /* DMC/CSR */ > > #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4) > > -- > > 2.25.4 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrj=C3=A4l=C3=A4 > Intel > --000000000000c6b07805bba7f5f0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Thu, Feb 11, 2021 at 1:= 29 PM Ville Syrj=C3=A4l=C3=A4 <ville.syrjala@linux.intel.com> wrote:
On Thu, Jan 28, 2021 at 11:24:13AM -08= 00, Matt Roper wrote:
> From: Nischal Varide <nischal.varide@intel.com>
>
> If the panel is 12bpc then Dithering is not enabled in the Legacy
> dithering block , instead its Enabled after the C1 CC1 pipe post
> color space conversion.For a 6bpc pannel Dithering is enabled in
> Legacy block.

Dithering is probably going to require a whole uapi bikeshed.
Not sure we can just enable it unilaterally.

Ccing dri-devel, and Mario who had issues with dithering in the
past...

Thanks for the cc Ville!

The problem with dithering on Intel is that various tested Intel gpu'= s (Ironlake, IvyBridge, Haswell, Skylake iirc.) are dithering when they sho= uldn't. If one has a standard 8 bpc framebuffer feeding into a standard= (legacy) 256 slots, 8 bit wide lut which was loaded with an identity mappi= ng, feeding into a standard 8 bpc video output (DVI/HDMI/DP), the expected = result is that pixels rendered into the framebuffer show up unmodified at t= he video output. What happens instead is that some dithering is needlessly = applied. This is bad for various neuroscience/medical research equipment th= at requires pixels to pass unmodified in a pure 8 bpc configuration, e.g., = because some digital info is color-encoded in-band in the rendered image to= control research hardware, a la "if rgb pixel (123, 12, 23) is detect= ed in the digital video stream, emit some trigger signal, or timestamp that= moment with a hw clock, or start or stop some scientific recording equipme= nt". Also there exist specialized visual stimulators to drive special = displays with more than 12 bpc, e.g., 16 bpc, and so they encode the 8MSB o= f 16 bpc color values in pixels in even columns, and the 8LSB in the odd co= lumns of the framebuffer. Unexpected dithering makes such equipment complet= ely unusable. By now I must have spent months of my life, just trying to de= al with dithering induced problems on different gpu's due to hw quirks = or bugs somewhere in the graphics stack.

Atm. = the intel kms driver disables dithering for anything with >=3D 8 bpc as = a fix for this harmful hardware quirk.

Ideally we= 'd have uapi that makes dithering controllable per connector (on/off/au= to, selectable depth), also in a way that those controls are exposed as Ran= dR output properties, easily controllable by X clients. And some safe defau= lt in case the client can't access the properties (like I'd expect = to happen with the dozens of Wayland compositors under the sun). Various dr= ivers had this over time, e.g., AMD classic kms path (if i don't misrem= ember) and nouveau, but some of it also got lost in the new atomic kms vari= ants, and Intel never exposed this.

Or maybe some metho= d that checks the values actually stored in the hw lut's, CTM etc. and = if the values suggest no dithering should be needed, disable the dithering.= E.g., if output depth is 8 bpc, one only needs dithering if the slots in t= he final active hw lut do have any meaningful values in the lower bits belo= w the top 8 MSB, ie. if the content is actually > 8 bpc net bit depth.

-mario

>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Nischal Varide <nischal.varide@intel.com>
> Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>=C2=A0 drivers/gpu/drm/i915/display/intel_color.c=C2=A0 =C2=A0| 16 ++++= ++++++++++++
>=C2=A0 drivers/gpu/drm/i915/display/intel_display.c |=C2=A0 9 ++++++++-=
>=C2=A0 drivers/gpu/drm/i915/i915_reg.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 |=C2=A0 3 ++-
>=C2=A0 3 files changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/= drm/i915/display/intel_color.c
> index ff7dcb7088bf..9a0572bbc5db 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1604,6 +1604,20 @@ static u32 icl_csc_mode(const struct intel_crtc= _state *crtc_state)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0return csc_mode;
>=C2=A0 }
>=C2=A0
> +static u32 dither_after_cc1_12bpc(const struct intel_crtc_state *crtc= _state)
> +{
> +=C2=A0 =C2=A0 =C2=A0u32 gamma_mode =3D crtc_state->gamma_mode;
> +=C2=A0 =C2=A0 =C2=A0struct drm_i915_private *i915 =3D to_i915(crtc_st= ate->uapi.crtc->dev);
> +
> +=C2=A0 =C2=A0 =C2=A0if (HAS_DISPLAY13(i915)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (!crtc_state->d= ither_force_disable &&
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(crtc_s= tate->pipe_bpp =3D=3D 36))
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0gamma_mode |=3D GAMMA_MODE_DITHER_AFTER_CC1;
> +=C2=A0 =C2=A0 =C2=A0}
> +
> +=C2=A0 =C2=A0 =C2=A0return gamma_mode;
> +}
> +
>=C2=A0 static int icl_color_check(struct intel_crtc_state *crtc_state)<= br> >=C2=A0 {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0int ret;
> @@ -1614,6 +1628,8 @@ static int icl_color_check(struct intel_crtc_sta= te *crtc_state)
>=C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0crtc_state->gamma_mode =3D icl_gamma_mode= (crtc_state);
>=C2=A0
> +=C2=A0 =C2=A0 =C2=A0crtc_state->gamma_mode =3D dither_after_cc1_12= bpc(crtc_state);
> +
>=C2=A0 =C2=A0 =C2=A0 =C2=A0crtc_state->csc_mode =3D icl_csc_mode(crt= c_state);
>=C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0crtc_state->preload_luts =3D intel_can_pr= eload_luts(crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gp= u/drm/i915/display/intel_display.c
> index 4dc4b1be0809..e3dbcd956fc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8098,9 +8098,15 @@ static void bdw_set_pipemisc(const struct intel= _crtc_state *crtc_state)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0
> -=C2=A0 =C2=A0 =C2=A0if (crtc_state->dither)
> +=C2=A0 =C2=A0 =C2=A0/*
> +=C2=A0 =C2=A0 =C2=A0 * If 12bpc panel then, Enables dithering after t= he CC1 pipe
> +=C2=A0 =C2=A0 =C2=A0 * post color space conversion and not here
> +=C2=A0 =C2=A0 =C2=A0 */
> +
> +=C2=A0 =C2=A0 =C2=A0if (crtc_state->dither && (crtc_state-= >pipe_bpp !=3D 36))
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0val |=3D PIPEMIS= C_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
>=C2=A0
> +
>=C2=A0 =C2=A0 =C2=A0 =C2=A0if (crtc_state->output_format =3D=3D INTE= L_OUTPUT_FORMAT_YCBCR420 ||
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0crtc_state->output_format = =3D=3D INTEL_OUTPUT_FORMAT_YCBCR444)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0val |=3D PIPEMIS= C_OUTPUT_COLORSPACE_YUV;
> @@ -10760,6 +10766,7 @@ intel_modeset_pipe_config(struct intel_atomic_= state *state,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 */
>=C2=A0 =C2=A0 =C2=A0 =C2=A0pipe_config->dither =3D (pipe_config->= pipe_bpp =3D=3D 6*3) &&
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0!pipe_config->= ;dither_force_disable;
> +
>=C2=A0 =C2=A0 =C2=A0 =C2=A0drm_dbg_kms(&i915->drm,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0&q= uot;hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ba= se_bpp, pipe_config->pipe_bpp, pipe_config->dither);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i9= 15_reg.h
> index 128b835c0adb..27f25214a839 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6132,7 +6132,7 @@ enum {
>=C2=A0 #define=C2=A0 =C2=A0PIPEMISC_DITHER_8_BPC=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0 << 5)
>=C2=A0 #define=C2=A0 =C2=A0PIPEMISC_DITHER_10_BPC=C2=A0 =C2=A0 =C2=A0(1= << 5)
>=C2=A0 #define=C2=A0 =C2=A0PIPEMISC_DITHER_6_BPC=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 (2 << 5)
> -#define=C2=A0 =C2=A0PIPEMISC_DITHER_12_BPC=C2=A0 =C2=A0 =C2=A0(3 <= < 5)
> +#define=C2=A0 =C2=A0PIPEMISC_DITHER_12_BPC=C2=A0 =C2=A0 =C2=A0(4 <= < 5)
>=C2=A0 #define=C2=A0 =C2=A0PIPEMISC_DITHER_ENABLE=C2=A0 =C2=A0 =C2=A0(1= << 4)
>=C2=A0 #define=C2=A0 =C2=A0PIPEMISC_DITHER_TYPE_MASK=C2=A0 (3 << = 2)
>=C2=A0 #define=C2=A0 =C2=A0PIPEMISC_DITHER_TYPE_SP=C2=A0 =C2=A0 (0 <= < 2)
> @@ -7668,6 +7668,7 @@ enum {
>=C2=A0 #define=C2=A0 GAMMA_MODE_MODE_12BIT=C2=A0 =C2=A0 =C2=A0 =C2=A0(2= << 0)
>=C2=A0 #define=C2=A0 GAMMA_MODE_MODE_SPLIT=C2=A0 =C2=A0 =C2=A0 =C2=A0(3= << 0) /* ivb-bdw */
>=C2=A0 #define=C2=A0 GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED=C2=A0 =C2=A0= =C2=A0 =C2=A0(3 << 0) /* icl + */
> +#define=C2=A0 GAMMA_MODE_DITHER_AFTER_CC1 (1 << 26)
>=C2=A0
>=C2=A0 /* DMC/CSR */
>=C2=A0 #define CSR_PROGRAM(i)=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0_MMIO(0x80000 + (i) * 4)
> --
> 2.25.4
>
> _______________________________________________
> Intel-gfx mailing list
> I= ntel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/l= istinfo/intel-gfx

--
Ville Syrj=C3=A4l=C3=A4
Intel
--000000000000c6b07805bba7f5f0-- --===============0535643410== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel --===============0535643410==-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.5 required=3.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A44C3C433DB for ; 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Thu, 18 Feb 2021 19:22:20 -0800 (PST) MIME-Version: 1.0 References: <20210128192413.1715802-1-matthew.d.roper@intel.com> <20210128192413.1715802-19-matthew.d.roper@intel.com> In-Reply-To: From: Mario Kleiner Date: Fri, 19 Feb 2021 04:22:09 +0100 Message-ID: To: =?UTF-8?B?VmlsbGUgU3lyasOkbMOk?= Subject: Re: [Intel-gfx] [PATCH 18/18] drm/i915/display13: Enabling dithering after the CC1 pipe X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx , Nischal Varide , dri-devel Content-Type: multipart/mixed; boundary="===============1420182985==" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" --===============1420182985== Content-Type: multipart/alternative; boundary="000000000000c6b07805bba7f5f0" --000000000000c6b07805bba7f5f0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Feb 11, 2021 at 1:29 PM Ville Syrj=C3=A4l=C3=A4 wrote: > On Thu, Jan 28, 2021 at 11:24:13AM -0800, Matt Roper wrote: > > From: Nischal Varide > > > > If the panel is 12bpc then Dithering is not enabled in the Legacy > > dithering block , instead its Enabled after the C1 CC1 pipe post > > color space conversion.For a 6bpc pannel Dithering is enabled in > > Legacy block. > > Dithering is probably going to require a whole uapi bikeshed. > Not sure we can just enable it unilaterally. > > Ccing dri-devel, and Mario who had issues with dithering in the > past... > > Thanks for the cc Ville! The problem with dithering on Intel is that various tested Intel gpu's (Ironlake, IvyBridge, Haswell, Skylake iirc.) are dithering when they shouldn't. If one has a standard 8 bpc framebuffer feeding into a standard (legacy) 256 slots, 8 bit wide lut which was loaded with an identity mapping, feeding into a standard 8 bpc video output (DVI/HDMI/DP), the expected result is that pixels rendered into the framebuffer show up unmodified at the video output. What happens instead is that some dithering is needlessly applied. This is bad for various neuroscience/medical research equipment that requires pixels to pass unmodified in a pure 8 bpc configuration, e.g., because some digital info is color-encoded in-band in the rendered image to control research hardware, a la "if rgb pixel (123, 12, 23) is detected in the digital video stream, emit some trigger signal, or timestamp that moment with a hw clock, or start or stop some scientific recording equipment". Also there exist specialized visual stimulators to drive special displays with more than 12 bpc, e.g., 16 bpc, and so they encode the 8MSB of 16 bpc color values in pixels in even columns, and the 8LSB in the odd columns of the framebuffer. Unexpected dithering makes such equipment completely unusable. By now I must have spent months of my life, just trying to deal with dithering induced problems on different gpu's due to hw quirks or bugs somewhere in the graphics stack. Atm. the intel kms driver disables dithering for anything with >=3D 8 bpc a= s a fix for this harmful hardware quirk. Ideally we'd have uapi that makes dithering controllable per connector (on/off/auto, selectable depth), also in a way that those controls are exposed as RandR output properties, easily controllable by X clients. And some safe default in case the client can't access the properties (like I'd expect to happen with the dozens of Wayland compositors under the sun). Various drivers had this over time, e.g., AMD classic kms path (if i don't misremember) and nouveau, but some of it also got lost in the new atomic kms variants, and Intel never exposed this. Or maybe some method that checks the values actually stored in the hw lut's, CTM etc. and if the values suggest no dithering should be needed, disable the dithering. E.g., if output depth is 8 bpc, one only needs dithering if the slots in the final active hw lut do have any meaningful values in the lower bits below the top 8 MSB, ie. if the content is actually > 8 bpc net bit depth. -mario > > > Cc: Uma Shankar > > Signed-off-by: Nischal Varide > > Signed-off-by: Bhanuprakash Modem > > Signed-off-by: Matt Roper > > --- > > drivers/gpu/drm/i915/display/intel_color.c | 16 ++++++++++++++++ > > drivers/gpu/drm/i915/display/intel_display.c | 9 ++++++++- > > drivers/gpu/drm/i915/i915_reg.h | 3 ++- > > 3 files changed, 26 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c > b/drivers/gpu/drm/i915/display/intel_color.c > > index ff7dcb7088bf..9a0572bbc5db 100644 > > --- a/drivers/gpu/drm/i915/display/intel_color.c > > +++ b/drivers/gpu/drm/i915/display/intel_color.c > > @@ -1604,6 +1604,20 @@ static u32 icl_csc_mode(const struct > intel_crtc_state *crtc_state) > > return csc_mode; > > } > > > > +static u32 dither_after_cc1_12bpc(const struct intel_crtc_state > *crtc_state) > > +{ > > + u32 gamma_mode =3D crtc_state->gamma_mode; > > + struct drm_i915_private *i915 =3D > to_i915(crtc_state->uapi.crtc->dev); > > + > > + if (HAS_DISPLAY13(i915)) { > > + if (!crtc_state->dither_force_disable && > > + (crtc_state->pipe_bpp =3D=3D 36)) > > + gamma_mode |=3D GAMMA_MODE_DITHER_AFTER_CC1; > > + } > > + > > + return gamma_mode; > > +} > > + > > static int icl_color_check(struct intel_crtc_state *crtc_state) > > { > > int ret; > > @@ -1614,6 +1628,8 @@ static int icl_color_check(struct intel_crtc_stat= e > *crtc_state) > > > > crtc_state->gamma_mode =3D icl_gamma_mode(crtc_state); > > > > + crtc_state->gamma_mode =3D dither_after_cc1_12bpc(crtc_state); > > + > > crtc_state->csc_mode =3D icl_csc_mode(crtc_state); > > > > crtc_state->preload_luts =3D intel_can_preload_luts(crtc_state); > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > > index 4dc4b1be0809..e3dbcd956fc6 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -8098,9 +8098,15 @@ static void bdw_set_pipemisc(const struct > intel_crtc_state *crtc_state) > > break; > > } > > > > - if (crtc_state->dither) > > + /* > > + * If 12bpc panel then, Enables dithering after the CC1 pipe > > + * post color space conversion and not here > > + */ > > + > > + if (crtc_state->dither && (crtc_state->pipe_bpp !=3D 36)) > > val |=3D PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP= ; > > > > + > > if (crtc_state->output_format =3D=3D INTEL_OUTPUT_FORMAT_YCBCR420= || > > crtc_state->output_format =3D=3D INTEL_OUTPUT_FORMAT_YCBCR444= ) > > val |=3D PIPEMISC_OUTPUT_COLORSPACE_YUV; > > @@ -10760,6 +10766,7 @@ intel_modeset_pipe_config(struct > intel_atomic_state *state, > > */ > > pipe_config->dither =3D (pipe_config->pipe_bpp =3D=3D 6*3) && > > !pipe_config->dither_force_disable; > > + > > drm_dbg_kms(&i915->drm, > > "hw max bpp: %i, pipe bpp: %i, dithering: %i\n", > > base_bpp, pipe_config->pipe_bpp, pipe_config->dither)= ; > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h > > index 128b835c0adb..27f25214a839 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -6132,7 +6132,7 @@ enum { > > #define PIPEMISC_DITHER_8_BPC (0 << 5) > > #define PIPEMISC_DITHER_10_BPC (1 << 5) > > #define PIPEMISC_DITHER_6_BPC (2 << 5) > > -#define PIPEMISC_DITHER_12_BPC (3 << 5) > > +#define PIPEMISC_DITHER_12_BPC (4 << 5) > > #define PIPEMISC_DITHER_ENABLE (1 << 4) > > #define PIPEMISC_DITHER_TYPE_MASK (3 << 2) > > #define PIPEMISC_DITHER_TYPE_SP (0 << 2) > > @@ -7668,6 +7668,7 @@ enum { > > #define GAMMA_MODE_MODE_12BIT (2 << 0) > > #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */ > > #define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + > */ > > +#define GAMMA_MODE_DITHER_AFTER_CC1 (1 << 26) > > > > /* DMC/CSR */ > > #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4) > > -- > > 2.25.4 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrj=C3=A4l=C3=A4 > Intel > --000000000000c6b07805bba7f5f0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Thu, Feb 11, 2021 at 1:= 29 PM Ville Syrj=C3=A4l=C3=A4 <ville.syrjala@linux.intel.com> wrote:
On Thu, Jan 28, 2021 at 11:24:13AM -08= 00, Matt Roper wrote:
> From: Nischal Varide <nischal.varide@intel.com>
>
> If the panel is 12bpc then Dithering is not enabled in the Legacy
> dithering block , instead its Enabled after the C1 CC1 pipe post
> color space conversion.For a 6bpc pannel Dithering is enabled in
> Legacy block.

Dithering is probably going to require a whole uapi bikeshed.
Not sure we can just enable it unilaterally.

Ccing dri-devel, and Mario who had issues with dithering in the
past...

Thanks for the cc Ville!

The problem with dithering on Intel is that various tested Intel gpu'= s (Ironlake, IvyBridge, Haswell, Skylake iirc.) are dithering when they sho= uldn't. If one has a standard 8 bpc framebuffer feeding into a standard= (legacy) 256 slots, 8 bit wide lut which was loaded with an identity mappi= ng, feeding into a standard 8 bpc video output (DVI/HDMI/DP), the expected = result is that pixels rendered into the framebuffer show up unmodified at t= he video output. What happens instead is that some dithering is needlessly = applied. This is bad for various neuroscience/medical research equipment th= at requires pixels to pass unmodified in a pure 8 bpc configuration, e.g., = because some digital info is color-encoded in-band in the rendered image to= control research hardware, a la "if rgb pixel (123, 12, 23) is detect= ed in the digital video stream, emit some trigger signal, or timestamp that= moment with a hw clock, or start or stop some scientific recording equipme= nt". Also there exist specialized visual stimulators to drive special = displays with more than 12 bpc, e.g., 16 bpc, and so they encode the 8MSB o= f 16 bpc color values in pixels in even columns, and the 8LSB in the odd co= lumns of the framebuffer. Unexpected dithering makes such equipment complet= ely unusable. By now I must have spent months of my life, just trying to de= al with dithering induced problems on different gpu's due to hw quirks = or bugs somewhere in the graphics stack.

Atm. = the intel kms driver disables dithering for anything with >=3D 8 bpc as = a fix for this harmful hardware quirk.

Ideally we= 'd have uapi that makes dithering controllable per connector (on/off/au= to, selectable depth), also in a way that those controls are exposed as Ran= dR output properties, easily controllable by X clients. And some safe defau= lt in case the client can't access the properties (like I'd expect = to happen with the dozens of Wayland compositors under the sun). Various dr= ivers had this over time, e.g., AMD classic kms path (if i don't misrem= ember) and nouveau, but some of it also got lost in the new atomic kms vari= ants, and Intel never exposed this.

Or maybe some metho= d that checks the values actually stored in the hw lut's, CTM etc. and = if the values suggest no dithering should be needed, disable the dithering.= E.g., if output depth is 8 bpc, one only needs dithering if the slots in t= he final active hw lut do have any meaningful values in the lower bits belo= w the top 8 MSB, ie. if the content is actually > 8 bpc net bit depth.

-mario

>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Nischal Varide <nischal.varide@intel.com>
> Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>=C2=A0 drivers/gpu/drm/i915/display/intel_color.c=C2=A0 =C2=A0| 16 ++++= ++++++++++++
>=C2=A0 drivers/gpu/drm/i915/display/intel_display.c |=C2=A0 9 ++++++++-=
>=C2=A0 drivers/gpu/drm/i915/i915_reg.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 |=C2=A0 3 ++-
>=C2=A0 3 files changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/= drm/i915/display/intel_color.c
> index ff7dcb7088bf..9a0572bbc5db 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1604,6 +1604,20 @@ static u32 icl_csc_mode(const struct intel_crtc= _state *crtc_state)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0return csc_mode;
>=C2=A0 }
>=C2=A0
> +static u32 dither_after_cc1_12bpc(const struct intel_crtc_state *crtc= _state)
> +{
> +=C2=A0 =C2=A0 =C2=A0u32 gamma_mode =3D crtc_state->gamma_mode;
> +=C2=A0 =C2=A0 =C2=A0struct drm_i915_private *i915 =3D to_i915(crtc_st= ate->uapi.crtc->dev);
> +
> +=C2=A0 =C2=A0 =C2=A0if (HAS_DISPLAY13(i915)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (!crtc_state->d= ither_force_disable &&
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(crtc_s= tate->pipe_bpp =3D=3D 36))
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0gamma_mode |=3D GAMMA_MODE_DITHER_AFTER_CC1;
> +=C2=A0 =C2=A0 =C2=A0}
> +
> +=C2=A0 =C2=A0 =C2=A0return gamma_mode;
> +}
> +
>=C2=A0 static int icl_color_check(struct intel_crtc_state *crtc_state)<= br> >=C2=A0 {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0int ret;
> @@ -1614,6 +1628,8 @@ static int icl_color_check(struct intel_crtc_sta= te *crtc_state)
>=C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0crtc_state->gamma_mode =3D icl_gamma_mode= (crtc_state);
>=C2=A0
> +=C2=A0 =C2=A0 =C2=A0crtc_state->gamma_mode =3D dither_after_cc1_12= bpc(crtc_state);
> +
>=C2=A0 =C2=A0 =C2=A0 =C2=A0crtc_state->csc_mode =3D icl_csc_mode(crt= c_state);
>=C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0crtc_state->preload_luts =3D intel_can_pr= eload_luts(crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gp= u/drm/i915/display/intel_display.c
> index 4dc4b1be0809..e3dbcd956fc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8098,9 +8098,15 @@ static void bdw_set_pipemisc(const struct intel= _crtc_state *crtc_state)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0
> -=C2=A0 =C2=A0 =C2=A0if (crtc_state->dither)
> +=C2=A0 =C2=A0 =C2=A0/*
> +=C2=A0 =C2=A0 =C2=A0 * If 12bpc panel then, Enables dithering after t= he CC1 pipe
> +=C2=A0 =C2=A0 =C2=A0 * post color space conversion and not here
> +=C2=A0 =C2=A0 =C2=A0 */
> +
> +=C2=A0 =C2=A0 =C2=A0if (crtc_state->dither && (crtc_state-= >pipe_bpp !=3D 36))
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0val |=3D PIPEMIS= C_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
>=C2=A0
> +
>=C2=A0 =C2=A0 =C2=A0 =C2=A0if (crtc_state->output_format =3D=3D INTE= L_OUTPUT_FORMAT_YCBCR420 ||
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0crtc_state->output_format = =3D=3D INTEL_OUTPUT_FORMAT_YCBCR444)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0val |=3D PIPEMIS= C_OUTPUT_COLORSPACE_YUV;
> @@ -10760,6 +10766,7 @@ intel_modeset_pipe_config(struct intel_atomic_= state *state,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 */
>=C2=A0 =C2=A0 =C2=A0 =C2=A0pipe_config->dither =3D (pipe_config->= pipe_bpp =3D=3D 6*3) &&
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0!pipe_config->= ;dither_force_disable;
> +
>=C2=A0 =C2=A0 =C2=A0 =C2=A0drm_dbg_kms(&i915->drm,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0&q= uot;hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ba= se_bpp, pipe_config->pipe_bpp, pipe_config->dither);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i9= 15_reg.h
> index 128b835c0adb..27f25214a839 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6132,7 +6132,7 @@ enum {
>=C2=A0 #define=C2=A0 =C2=A0PIPEMISC_DITHER_8_BPC=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0 << 5)
>=C2=A0 #define=C2=A0 =C2=A0PIPEMISC_DITHER_10_BPC=C2=A0 =C2=A0 =C2=A0(1= << 5)
>=C2=A0 #define=C2=A0 =C2=A0PIPEMISC_DITHER_6_BPC=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 (2 << 5)
> -#define=C2=A0 =C2=A0PIPEMISC_DITHER_12_BPC=C2=A0 =C2=A0 =C2=A0(3 <= < 5)
> +#define=C2=A0 =C2=A0PIPEMISC_DITHER_12_BPC=C2=A0 =C2=A0 =C2=A0(4 <= < 5)
>=C2=A0 #define=C2=A0 =C2=A0PIPEMISC_DITHER_ENABLE=C2=A0 =C2=A0 =C2=A0(1= << 4)
>=C2=A0 #define=C2=A0 =C2=A0PIPEMISC_DITHER_TYPE_MASK=C2=A0 (3 << = 2)
>=C2=A0 #define=C2=A0 =C2=A0PIPEMISC_DITHER_TYPE_SP=C2=A0 =C2=A0 (0 <= < 2)
> @@ -7668,6 +7668,7 @@ enum {
>=C2=A0 #define=C2=A0 GAMMA_MODE_MODE_12BIT=C2=A0 =C2=A0 =C2=A0 =C2=A0(2= << 0)
>=C2=A0 #define=C2=A0 GAMMA_MODE_MODE_SPLIT=C2=A0 =C2=A0 =C2=A0 =C2=A0(3= << 0) /* ivb-bdw */
>=C2=A0 #define=C2=A0 GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED=C2=A0 =C2=A0= =C2=A0 =C2=A0(3 << 0) /* icl + */
> +#define=C2=A0 GAMMA_MODE_DITHER_AFTER_CC1 (1 << 26)
>=C2=A0
>=C2=A0 /* DMC/CSR */
>=C2=A0 #define CSR_PROGRAM(i)=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0_MMIO(0x80000 + (i) * 4)
> --
> 2.25.4
>
> _______________________________________________
> Intel-gfx mailing list
> I= ntel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/l= istinfo/intel-gfx

--
Ville Syrj=C3=A4l=C3=A4
Intel
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