From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.4 required=3.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,MIME_HTML_MOSTLY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87C4EC433DB for ; Wed, 10 Feb 2021 21:06:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 39E9364E16 for ; Wed, 10 Feb 2021 21:06:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 39E9364E16 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1EDA58914E; Wed, 10 Feb 2021 21:06:53 +0000 (UTC) Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by gabe.freedesktop.org (Postfix) with ESMTPS id 812686ECDE; Wed, 10 Feb 2021 21:06:51 +0000 (UTC) Received: by mail-ed1-x536.google.com with SMTP id t5so4651347eds.12; Wed, 10 Feb 2021 13:06:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=FrGcjihHtHTDqMK8qS//KOQi9Pnx0xxc4S99TbHEKVU=; b=bZl/3bJZmk5RSlcmoT/d4XtTc2Wn3xGjMj0KurYjuqzKP4zBw+bc9QrK5efwAIIOe6 TwLkyTbpGG62cmzPc6yD2IOBQebOJAdMPe9YDMVFu6QQY+dLPNyqqPbKV0p968NOKC5d nUNZB4C8i9imYqR02Yr92gp8e17YYrgkHNhIcmEyn5ViChdgAw1W4wIawB2H9TndL9kP 6PfFGoHogcMdqZaK167oPfusEMqTyrfEoDpBsFf2QTh4jbxvNO2O6rdeptjKu0iYEVj3 T1IU8uOR8Db5V+pvr3BUsvmd//QfggGxnW/x5VLbKa0LMryogTVAOHDhZBNUBCy7A1OJ MvWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=FrGcjihHtHTDqMK8qS//KOQi9Pnx0xxc4S99TbHEKVU=; b=KYIRKwUoAGQ/JYZ+ONEWXN69m1yE2Aurn7dHDafEYYStzw+KKO/PNEZjQGv+YoBTHd JzUTpR49lshDlMVSBY9379nVUguRrfknDIGRcgMP0t+vNwcOt3WE7Vt0KFdgF7cycyZA xGQESUWOLBu1IOuBDblZXz9bRkIYRal9/9Y3REz97lcpVYhJntnZf0eYsXSvipk4u5ub Tq1OkXaZ+jxxqs2uqFLQWibdx2sm+4HSbL0QGRIMzQYhHLJUv/aAvibRcBXp8ysYrZX9 Yji5ycJPAkL4UUqtzfZUpn4KpauV0/JJLLsGdNzQ7T42dPQyKZdFlaiqrtbmaK7ddx4E +ovQ== X-Gm-Message-State: AOAM533m/gASF6dyDFAwySRlvqnZXZoguWbEah/PbrOMh3a7LANJ7d1F CkihCT4tzbht1bOrgfgajncbgTO83lp7yT+59Hso0RDm X-Google-Smtp-Source: ABdhPJw3d0UoQNz1PuYGj9utgFV+Yk2Ofq33h8ChNMAyTB34qOS9ILkDvT4y7/HEcqQhMbCxVGqGr9Y1LC4DzCtzc6Q= X-Received: by 2002:aa7:d808:: with SMTP id v8mr5065111edq.380.1612991210061; Wed, 10 Feb 2021 13:06:50 -0800 (PST) MIME-Version: 1.0 References: <20210121061704.21090-1-mario.kleiner.de@gmail.com> <20210121061704.21090-3-mario.kleiner.de@gmail.com> <25c30592-43aa-50f6-8904-63f983391f56@amd.com> In-Reply-To: From: Mario Kleiner Date: Wed, 10 Feb 2021 22:06:38 +0100 Message-ID: Subject: Re: [PATCH 2/2] drm/amd/display: Fix HDMI deep color output for DCE 6-11. To: "Kazlauskas, Nicholas" X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Deucher, Alexander" , Maling list - DRI developers , amd-gfx list Content-Type: multipart/mixed; boundary="===============1579110645==" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" --===============1579110645== Content-Type: multipart/alternative; boundary="0000000000001a038c05bb01c899" --0000000000001a038c05bb01c899 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Ping. Any bit of info appreciated wrt. the DCE-11.2+ situation. -mario On Mon, Jan 25, 2021 at 8:24 PM Mario Kleiner wrote: > Thanks Alex and Nicholas! Brings quite a bit of extra shiny to those olde= r > asics :) > > Nicholas, any thoughts on my cover-letter wrt. why a similar patch (that = I > wrote and tested to no good or bad effect) not seem to be needed on DCN, > and probably not DCE-11.2+ either? Is what is left in DC for those asic's > just dead code? My Atombios disassembly sort of pointed into that > direction, but reading disassembly is not easy on the brain, and my brain > was getting quite mushy towards the end of digging through all the code. = So > some official statement would add peace of mind on my side. Is there a > certain DCE version at which your team starts validating output precision= / > HDR etc. on hw? > > Thanks, > -mario > > > On Mon, Jan 25, 2021 at 8:16 PM Kazlauskas, Nicholas < > nicholas.kazlauskas@amd.com> wrote: > >> On 2021-01-25 12:57 p.m., Alex Deucher wrote: >> > On Thu, Jan 21, 2021 at 1:17 AM Mario Kleiner >> > wrote: >> >> >> >> This fixes corrupted display output in HDMI deep color >> >> 10/12 bpc mode at least as observed on AMD Mullins, DCE-8.3. >> >> >> >> It will hopefully also provide fixes for other DCE's up to >> >> DCE-11, assuming those will need similar fixes, but i could >> >> not test that for HDMI due to lack of suitable hw, so viewer >> >> discretion is advised. >> >> >> >> dce110_stream_encoder_hdmi_set_stream_attribute() is used for >> >> HDMI setup on all DCE's and is missing color_depth assignment. >> >> >> >> dce110_program_pix_clk() is used for pixel clock setup on HDMI >> >> for DCE 6-11, and is missing color_depth assignment. >> >> >> >> Additionally some of the underlying Atombios specific encoder >> >> and pixelclock setup functions are missing code which is in >> >> the classic amdgpu kms modesetting path and the in the radeon >> >> kms driver for DCE6/DCE8. >> >> >> >> encoder_control_digx_v3() - Was missing setup code wrt. amdgpu >> >> and radeon kms classic drivers. Added here, but untested due to >> >> lack of suitable test hw. >> >> >> >> encoder_control_digx_v4() - Added missing setup code. >> >> Successfully tested on AMD mullins / DCE-8.3 with HDMI deep color >> >> output at 10 bpc and 12 bpc. >> >> >> >> Note that encoder_control_digx_v5() has proper setup code in place >> >> and is used, e.g., by DCE-11.2, but this code wasn't used for deep >> >> color setup due to the missing cntl.color_depth setup in the calling >> >> function for HDMI. >> >> >> >> set_pixel_clock_v5() - Missing setup code wrt. classic amdgpu/radeon >> >> kms. Added here, but untested due to lack of hw. >> >> >> >> set_pixel_clock_v6() - Missing setup code added. Successfully tested >> >> on AMD mullins DCE-8.3. This fixes corrupted display output at HDMI >> >> deep color output with 10 bpc or 12 bpc. >> >> >> >> Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)") >> >> >> >> Signed-off-by: Mario Kleiner >> >> Cc: Harry Wentland >> > >> > These make sense. I've applied the series. I'll let the display guys >> > gauge the other points in your cover letter. >> > >> > Alex >> >> I don't have any concerns with this patch. >> >> Even though it's already applied feel free to have my: >> >> Reviewed-by: Nicholas Kazlauskas >> >> Regards, >> Nicholas Kazlauskas >> >> > >> > >> >> --- >> >> .../drm/amd/display/dc/bios/command_table.c | 61 >> +++++++++++++++++++ >> >> .../drm/amd/display/dc/dce/dce_clock_source.c | 14 +++++ >> >> .../amd/display/dc/dce/dce_stream_encoder.c | 1 + >> >> 3 files changed, 76 insertions(+) >> >> >> >> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c >> b/drivers/gpu/drm/amd/display/dc/bios/command_table.c >> >> index 070459e3e407..afc10b954ffa 100644 >> >> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c >> >> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c >> >> @@ -245,6 +245,23 @@ static enum bp_result encoder_control_digx_v3( >> >> cntl->enable_dp_audio); >> >> params.ucLaneNum =3D (uint8_t)(cntl->lanes_number); >> >> >> >> + switch (cntl->color_depth) { >> >> + case COLOR_DEPTH_888: >> >> + params.ucBitPerColor =3D PANEL_8BIT_PER_COLOR; >> >> + break; >> >> + case COLOR_DEPTH_101010: >> >> + params.ucBitPerColor =3D PANEL_10BIT_PER_COLOR; >> >> + break; >> >> + case COLOR_DEPTH_121212: >> >> + params.ucBitPerColor =3D PANEL_12BIT_PER_COLOR; >> >> + break; >> >> + case COLOR_DEPTH_161616: >> >> + params.ucBitPerColor =3D PANEL_16BIT_PER_COLOR; >> >> + break; >> >> + default: >> >> + break; >> >> + } >> >> + >> >> if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params)) >> >> result =3D BP_RESULT_OK; >> >> >> >> @@ -274,6 +291,23 @@ static enum bp_result encoder_control_digx_v4( >> >> cntl->enable_dp_audio)); >> >> params.ucLaneNum =3D (uint8_t)(cntl->lanes_number); >> >> >> >> + switch (cntl->color_depth) { >> >> + case COLOR_DEPTH_888: >> >> + params.ucBitPerColor =3D PANEL_8BIT_PER_COLOR; >> >> + break; >> >> + case COLOR_DEPTH_101010: >> >> + params.ucBitPerColor =3D PANEL_10BIT_PER_COLOR; >> >> + break; >> >> + case COLOR_DEPTH_121212: >> >> + params.ucBitPerColor =3D PANEL_12BIT_PER_COLOR; >> >> + break; >> >> + case COLOR_DEPTH_161616: >> >> + params.ucBitPerColor =3D PANEL_16BIT_PER_COLOR; >> >> + break; >> >> + default: >> >> + break; >> >> + } >> >> + >> >> if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params)) >> >> result =3D BP_RESULT_OK; >> >> >> >> @@ -1057,6 +1091,19 @@ static enum bp_result set_pixel_clock_v5( >> >> * driver choose program it itself, i.e. here we >> program it >> >> * to 888 by default. >> >> */ >> >> + if (bp_params->signal_type =3D=3D SIGNAL_TYPE_HDMI_TY= PE_A) >> >> + switch (bp_params->color_depth) { >> >> + case TRANSMITTER_COLOR_DEPTH_30: >> >> + /* yes this is correct, the atom >> define is wrong */ >> >> + clk.sPCLKInput.ucMiscInfo |=3D >> PIXEL_CLOCK_V5_MISC_HDMI_32BPP; >> >> + break; >> >> + case TRANSMITTER_COLOR_DEPTH_36: >> >> + /* yes this is correct, the atom >> define is wrong */ >> >> + clk.sPCLKInput.ucMiscInfo |=3D >> PIXEL_CLOCK_V5_MISC_HDMI_30BPP; >> >> + break; >> >> + default: >> >> + break; >> >> + } >> >> >> >> if (EXEC_BIOS_CMD_TABLE(SetPixelClock, clk)) >> >> result =3D BP_RESULT_OK; >> >> @@ -1135,6 +1182,20 @@ static enum bp_result set_pixel_clock_v6( >> >> * driver choose program it itself, i.e. here we pas= s >> required >> >> * target rate that includes deep color. >> >> */ >> >> + if (bp_params->signal_type =3D=3D SIGNAL_TYPE_HDMI_TY= PE_A) >> >> + switch (bp_params->color_depth) { >> >> + case TRANSMITTER_COLOR_DEPTH_30: >> >> + clk.sPCLKInput.ucMiscInfo |=3D >> PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6; >> >> + break; >> >> + case TRANSMITTER_COLOR_DEPTH_36: >> >> + clk.sPCLKInput.ucMiscInfo |=3D >> PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6; >> >> + break; >> >> + case TRANSMITTER_COLOR_DEPTH_48: >> >> + clk.sPCLKInput.ucMiscInfo |=3D >> PIXEL_CLOCK_V6_MISC_HDMI_48BPP; >> >> + break; >> >> + default: >> >> + break; >> >> + } >> >> >> >> if (EXEC_BIOS_CMD_TABLE(SetPixelClock, clk)) >> >> result =3D BP_RESULT_OK; >> >> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c >> b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c >> >> index fb733f573715..466f8f5803c9 100644 >> >> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c >> >> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c >> >> @@ -871,6 +871,20 @@ static bool dce110_program_pix_clk( >> >> bp_pc_params.flags.SET_EXTERNAL_REF_DIV_SRC =3D >> >> >> pll_settings->use_external_clk; >> >> >> >> + switch (pix_clk_params->color_depth) { >> >> + case COLOR_DEPTH_101010: >> >> + bp_pc_params.color_depth =3D TRANSMITTER_COLOR_DEPTH_= 30; >> >> + break; >> >> + case COLOR_DEPTH_121212: >> >> + bp_pc_params.color_depth =3D TRANSMITTER_COLOR_DEPTH_= 36; >> >> + break; >> >> + case COLOR_DEPTH_161616: >> >> + bp_pc_params.color_depth =3D TRANSMITTER_COLOR_DEPTH_= 48; >> >> + break; >> >> + default: >> >> + break; >> >> + } >> >> + >> >> if (clk_src->bios->funcs->set_pixel_clock( >> >> clk_src->bios, &bp_pc_params) !=3D BP_RESULT= _OK) >> >> return false; >> >> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c >> b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c >> >> index ada57f745fd7..19e380e0a330 100644 >> >> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c >> >> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c >> >> @@ -564,6 +564,7 @@ static void >> dce110_stream_encoder_hdmi_set_stream_attribute( >> >> cntl.enable_dp_audio =3D enable_audio; >> >> cntl.pixel_clock =3D actual_pix_clk_khz; >> >> cntl.lanes_number =3D LANE_COUNT_FOUR; >> >> + cntl.color_depth =3D crtc_timing->display_color_depth; >> >> >> >> if (enc110->base.bp->funcs->encoder_control( >> >> enc110->base.bp, &cntl) !=3D BP_RESULT_OK) >> >> -- >> >> 2.25.1 >> >> >> >> _______________________________________________ >> >> dri-devel mailing list >> >> dri-devel@lists.freedesktop.org >> >> >> https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Flist= s.freedesktop.org%2Fmailman%2Flistinfo%2Fdri-devel&data=3D04%7C01%7Cnic= holas.kazlauskas%40amd.com%7C598b2b5e841940b8c27708d8c15aa80d%7C3dd8961fe48= 84e608e11a82d994e183d%7C0%7C0%7C637471942408643835%7CUnknown%7CTWFpbGZsb3d8= eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&a= mp;sdata=3Db9C3Xi%2F2RmNsGyGUN5oBF8U%2BuGyt2w4jUZ2dK8NM4AY%3D&reserved= =3D0 >> > _______________________________________________ >> > dri-devel mailing list >> > dri-devel@lists.freedesktop.org >> > >> https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Flist= s.freedesktop.org%2Fmailman%2Flistinfo%2Fdri-devel&data=3D04%7C01%7Cnic= holas.kazlauskas%40amd.com%7C598b2b5e841940b8c27708d8c15aa80d%7C3dd8961fe48= 84e608e11a82d994e183d%7C0%7C0%7C637471942408643835%7CUnknown%7CTWFpbGZsb3d8= eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&a= mp;sdata=3Db9C3Xi%2F2RmNsGyGUN5oBF8U%2BuGyt2w4jUZ2dK8NM4AY%3D&reserved= =3D0 >> > >> >> --0000000000001a038c05bb01c899 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Ping. Any bit of info appreciated wrt. the DCE-11.2+ situa= tion.
-mario

On Mon, Jan 25, 2021 at 8:24 PM Mario Kleiner <mario.kleiner.de@gmail.com&g= t; wrote:
Thanks Alex and Nicholas! Brings quite a bit of extra shiny= to those older asics :)

Nicholas, any thoughts on= my cover-letter wrt. why a similar patch (that I wrote and tested to no go= od or bad effect) not seem to be needed on DCN, and probably not DCE-11.2+ = either? Is what is left in DC for those asic's just dead code? My Atomb= ios disassembly sort of pointed into that direction, but reading disassembl= y is not easy on the brain, and my brain was getting quite mushy towards th= e end of digging through all the code. So some official statement would add= peace of mind on my side. Is there a certain DCE version at which your tea= m starts validating output precision / HDR etc. on hw?

Thanks,
-mario


On Mon, Jan 25, 2021= at 8:16 PM Kazlauskas, Nicholas <nicholas.kazlauskas@amd.com> wrote:
On 2021-01-25 12:57 p= .m., Alex Deucher wrote:
> On Thu, Jan 21, 2021 at 1:17 AM Mario Kleiner
> <ma= rio.kleiner.de@gmail.com> wrote:
>>
>> This fixes corrupted display output in HDMI deep color
>> 10/12 bpc mode at least as observed on AMD Mullins, DCE-8.3.
>>
>> It will hopefully also provide fixes for other DCE's up to
>> DCE-11, assuming those will need similar fixes, but i could
>> not test that for HDMI due to lack of suitable hw, so viewer
>> discretion is advised.
>>
>> dce110_stream_encoder_hdmi_set_stream_attribute() is used for
>> HDMI setup on all DCE's and is missing color_depth assignment.=
>>
>> dce110_program_pix_clk() is used for pixel clock setup on HDMI
>> for DCE 6-11, and is missing color_depth assignment.
>>
>> Additionally some of the underlying Atombios specific encoder
>> and pixelclock setup functions are missing code which is in
>> the classic amdgpu kms modesetting path and the in the radeon
>> kms driver for DCE6/DCE8.
>>
>> encoder_control_digx_v3() - Was missing setup code wrt. amdgpu
>> and radeon kms classic drivers. Added here, but untested due to >> lack of suitable test hw.
>>
>> encoder_control_digx_v4() - Added missing setup code.
>> Successfully tested on AMD mullins / DCE-8.3 with HDMI deep color<= br> >> output at 10 bpc and 12 bpc.
>>
>> Note that encoder_control_digx_v5() has proper setup code in place=
>> and is used, e.g., by DCE-11.2, but this code wasn't used for = deep
>> color setup due to the missing cntl.color_depth setup in the calli= ng
>> function for HDMI.
>>
>> set_pixel_clock_v5() - Missing setup code wrt. classic amdgpu/rade= on
>> kms. Added here, but untested due to lack of hw.
>>
>> set_pixel_clock_v6() - Missing setup code added. Successfully test= ed
>> on AMD mullins DCE-8.3. This fixes corrupted display output at HDM= I
>> deep color output with 10 bpc or 12 bpc.
>>
>> Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)&= quot;)
>>
>> Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
>> Cc: Harry Wentland <harry.wentland@amd.com>
>
> These make sense. I've applied the series.=C2=A0 I'll let the = display guys
> gauge the other points in your cover letter.
>
> Alex

I don't have any concerns with this patch.

Even though it's already applied feel free to have my:

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>

Regards,
Nicholas Kazlauskas

>
>
>> ---
>>=C2=A0 =C2=A0.../drm/amd/display/dc/bios/command_table.c=C2=A0 =C2= =A0| 61 +++++++++++++++++++
>>=C2=A0 =C2=A0.../drm/amd/display/dc/dce/dce_clock_source.c | 14 +++= ++
>>=C2=A0 =C2=A0.../amd/display/dc/dce/dce_stream_encoder.c=C2=A0 =C2= =A0|=C2=A0 1 +
>>=C2=A0 =C2=A03 files changed, 76 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b= /drivers/gpu/drm/amd/display/dc/bios/command_table.c
>> index 070459e3e407..afc10b954ffa 100644
>> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
>> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
>> @@ -245,6 +245,23 @@ static enum bp_result encoder_control_digx_v3= (
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 cntl->enable_dp_audio);
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 params.ucLaneNum =3D (uint8_t)(c= ntl->lanes_number);
>>
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0switch (cntl->color_depth) {
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0case COLOR_DEPTH_888:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0params.ucB= itPerColor =3D PANEL_8BIT_PER_COLOR;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0case COLOR_DEPTH_101010:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0params.ucB= itPerColor =3D PANEL_10BIT_PER_COLOR;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0case COLOR_DEPTH_121212:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0params.ucB= itPerColor =3D PANEL_12BIT_PER_COLOR;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0case COLOR_DEPTH_161616:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0params.ucB= itPerColor =3D PANEL_16BIT_PER_COLOR;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0default:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>> +
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (EXEC_BIOS_CMD_TABLE(DIGxEnco= derControl, params))
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 resu= lt =3D BP_RESULT_OK;
>>
>> @@ -274,6 +291,23 @@ static enum bp_result encoder_control_digx_v4= (
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 cntl->enable_dp_audio));
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 params.ucLaneNum =3D (uint8_t)(c= ntl->lanes_number);
>>
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0switch (cntl->color_depth) {
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0case COLOR_DEPTH_888:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0params.ucB= itPerColor =3D PANEL_8BIT_PER_COLOR;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0case COLOR_DEPTH_101010:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0params.ucB= itPerColor =3D PANEL_10BIT_PER_COLOR;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0case COLOR_DEPTH_121212:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0params.ucB= itPerColor =3D PANEL_12BIT_PER_COLOR;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0case COLOR_DEPTH_161616:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0params.ucB= itPerColor =3D PANEL_16BIT_PER_COLOR;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0default:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>> +
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (EXEC_BIOS_CMD_TABLE(DIGxEnco= derControl, params))
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 resu= lt =3D BP_RESULT_OK;
>>
>> @@ -1057,6 +1091,19 @@ static enum bp_result set_pixel_clock_v5( >>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0* driver choose program it itself, i.e. here we program it
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0* to 888 by default.
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0*/
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (bp_par= ams->signal_type =3D=3D SIGNAL_TYPE_HDMI_TYPE_A)
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0switch (bp_params->color_depth) {
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0case TRANSMITTER_COLOR_DEPTH_30:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* yes this is correct, the= atom define is wrong */
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0clk.sPCLKInput.ucMiscInfo |= =3D PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0case TRANSMITTER_COLOR_DEPTH_36:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* yes this is correct, the= atom define is wrong */
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0clk.sPCLKInput.ucMiscInfo |= =3D PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0default:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0}
>>
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (= EXEC_BIOS_CMD_TABLE(SetPixelClock, clk))
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 result =3D BP_RESULT_OK;
>> @@ -1135,6 +1182,20 @@ static enum bp_result set_pixel_clock_v6( >>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0* driver choose program it itself, i.e. here we pass required
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0* target rate that includes deep color.
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0*/
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (bp_par= ams->signal_type =3D=3D SIGNAL_TYPE_HDMI_TYPE_A)
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0switch (bp_params->color_depth) {
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0case TRANSMITTER_COLOR_DEPTH_30:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0clk.sPCLKInput.ucMiscInfo |= =3D PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0case TRANSMITTER_COLOR_DEPTH_36:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0clk.sPCLKInput.ucMiscInfo |= =3D PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0case TRANSMITTER_COLOR_DEPTH_48:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0clk.sPCLKInput.ucMiscInfo |= =3D PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0default:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0}
>>
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (= EXEC_BIOS_CMD_TABLE(SetPixelClock, clk))
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 result =3D BP_RESULT_OK;
>> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c= b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
>> index fb733f573715..466f8f5803c9 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
>> @@ -871,6 +871,20 @@ static bool dce110_program_pix_clk(
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bp_pc_params.flags.SET_EXTERNAL_= REF_DIV_SRC =3D
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 pll_settings->use_external_clk;
>>
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0switch (pix_clk_params->color_depth= ) {
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0case COLOR_DEPTH_101010:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0bp_pc_para= ms.color_depth =3D TRANSMITTER_COLOR_DEPTH_30;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0case COLOR_DEPTH_121212:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0bp_pc_para= ms.color_depth =3D TRANSMITTER_COLOR_DEPTH_36;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0case COLOR_DEPTH_161616:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0bp_pc_para= ms.color_depth =3D TRANSMITTER_COLOR_DEPTH_48;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0default:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>> +
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (clk_src->bios->funcs-&= gt;set_pixel_clock(
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 clk_src->bios, &bp_pc_params) !=3D BP_RESUL= T_OK)
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 retu= rn false;
>> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder= .c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
>> index ada57f745fd7..19e380e0a330 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
>> @@ -564,6 +564,7 @@ static void dce110_stream_encoder_hdmi_set_str= eam_attribute(
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cntl.enable_dp_audio =3D enable_= audio;
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cntl.pixel_clock =3D actual_pix_= clk_khz;
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cntl.lanes_number =3D LANE_COUNT= _FOUR;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0cntl.color_depth =3D crtc_timing->d= isplay_color_depth;
>>
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (enc110->base.bp->funcs= ->encoder_control(
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 enc110->base.bp, &cntl) !=3D BP_RESULT_OK)<= br> >> --
>> 2.25.1
>>
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--0000000000001a038c05bb01c899-- --===============1579110645== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel --===============1579110645==-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.4 required=3.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,MIME_HTML_MOSTLY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37F57C433E0 for ; Wed, 10 Feb 2021 21:06:59 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EE9C964E16 for ; Wed, 10 Feb 2021 21:06:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EE9C964E16 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=amd-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7AD1189450; Wed, 10 Feb 2021 21:06:53 +0000 (UTC) Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by gabe.freedesktop.org (Postfix) with ESMTPS id 812686ECDE; Wed, 10 Feb 2021 21:06:51 +0000 (UTC) Received: by mail-ed1-x536.google.com with SMTP id t5so4651347eds.12; Wed, 10 Feb 2021 13:06:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=FrGcjihHtHTDqMK8qS//KOQi9Pnx0xxc4S99TbHEKVU=; b=bZl/3bJZmk5RSlcmoT/d4XtTc2Wn3xGjMj0KurYjuqzKP4zBw+bc9QrK5efwAIIOe6 TwLkyTbpGG62cmzPc6yD2IOBQebOJAdMPe9YDMVFu6QQY+dLPNyqqPbKV0p968NOKC5d nUNZB4C8i9imYqR02Yr92gp8e17YYrgkHNhIcmEyn5ViChdgAw1W4wIawB2H9TndL9kP 6PfFGoHogcMdqZaK167oPfusEMqTyrfEoDpBsFf2QTh4jbxvNO2O6rdeptjKu0iYEVj3 T1IU8uOR8Db5V+pvr3BUsvmd//QfggGxnW/x5VLbKa0LMryogTVAOHDhZBNUBCy7A1OJ MvWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=FrGcjihHtHTDqMK8qS//KOQi9Pnx0xxc4S99TbHEKVU=; b=KYIRKwUoAGQ/JYZ+ONEWXN69m1yE2Aurn7dHDafEYYStzw+KKO/PNEZjQGv+YoBTHd JzUTpR49lshDlMVSBY9379nVUguRrfknDIGRcgMP0t+vNwcOt3WE7Vt0KFdgF7cycyZA xGQESUWOLBu1IOuBDblZXz9bRkIYRal9/9Y3REz97lcpVYhJntnZf0eYsXSvipk4u5ub Tq1OkXaZ+jxxqs2uqFLQWibdx2sm+4HSbL0QGRIMzQYhHLJUv/aAvibRcBXp8ysYrZX9 Yji5ycJPAkL4UUqtzfZUpn4KpauV0/JJLLsGdNzQ7T42dPQyKZdFlaiqrtbmaK7ddx4E +ovQ== X-Gm-Message-State: AOAM533m/gASF6dyDFAwySRlvqnZXZoguWbEah/PbrOMh3a7LANJ7d1F CkihCT4tzbht1bOrgfgajncbgTO83lp7yT+59Hso0RDm X-Google-Smtp-Source: ABdhPJw3d0UoQNz1PuYGj9utgFV+Yk2Ofq33h8ChNMAyTB34qOS9ILkDvT4y7/HEcqQhMbCxVGqGr9Y1LC4DzCtzc6Q= X-Received: by 2002:aa7:d808:: with SMTP id v8mr5065111edq.380.1612991210061; Wed, 10 Feb 2021 13:06:50 -0800 (PST) MIME-Version: 1.0 References: <20210121061704.21090-1-mario.kleiner.de@gmail.com> <20210121061704.21090-3-mario.kleiner.de@gmail.com> <25c30592-43aa-50f6-8904-63f983391f56@amd.com> In-Reply-To: From: Mario Kleiner Date: Wed, 10 Feb 2021 22:06:38 +0100 Message-ID: Subject: Re: [PATCH 2/2] drm/amd/display: Fix HDMI deep color output for DCE 6-11. To: "Kazlauskas, Nicholas" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alex Deucher , "Deucher, Alexander" , Maling list - DRI developers , amd-gfx list Content-Type: multipart/mixed; boundary="===============0671984977==" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" --===============0671984977== Content-Type: multipart/alternative; boundary="0000000000001a038c05bb01c899" --0000000000001a038c05bb01c899 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Ping. Any bit of info appreciated wrt. the DCE-11.2+ situation. -mario On Mon, Jan 25, 2021 at 8:24 PM Mario Kleiner wrote: > Thanks Alex and Nicholas! Brings quite a bit of extra shiny to those olde= r > asics :) > > Nicholas, any thoughts on my cover-letter wrt. why a similar patch (that = I > wrote and tested to no good or bad effect) not seem to be needed on DCN, > and probably not DCE-11.2+ either? Is what is left in DC for those asic's > just dead code? My Atombios disassembly sort of pointed into that > direction, but reading disassembly is not easy on the brain, and my brain > was getting quite mushy towards the end of digging through all the code. = So > some official statement would add peace of mind on my side. Is there a > certain DCE version at which your team starts validating output precision= / > HDR etc. on hw? > > Thanks, > -mario > > > On Mon, Jan 25, 2021 at 8:16 PM Kazlauskas, Nicholas < > nicholas.kazlauskas@amd.com> wrote: > >> On 2021-01-25 12:57 p.m., Alex Deucher wrote: >> > On Thu, Jan 21, 2021 at 1:17 AM Mario Kleiner >> > wrote: >> >> >> >> This fixes corrupted display output in HDMI deep color >> >> 10/12 bpc mode at least as observed on AMD Mullins, DCE-8.3. >> >> >> >> It will hopefully also provide fixes for other DCE's up to >> >> DCE-11, assuming those will need similar fixes, but i could >> >> not test that for HDMI due to lack of suitable hw, so viewer >> >> discretion is advised. >> >> >> >> dce110_stream_encoder_hdmi_set_stream_attribute() is used for >> >> HDMI setup on all DCE's and is missing color_depth assignment. >> >> >> >> dce110_program_pix_clk() is used for pixel clock setup on HDMI >> >> for DCE 6-11, and is missing color_depth assignment. >> >> >> >> Additionally some of the underlying Atombios specific encoder >> >> and pixelclock setup functions are missing code which is in >> >> the classic amdgpu kms modesetting path and the in the radeon >> >> kms driver for DCE6/DCE8. >> >> >> >> encoder_control_digx_v3() - Was missing setup code wrt. amdgpu >> >> and radeon kms classic drivers. Added here, but untested due to >> >> lack of suitable test hw. >> >> >> >> encoder_control_digx_v4() - Added missing setup code. >> >> Successfully tested on AMD mullins / DCE-8.3 with HDMI deep color >> >> output at 10 bpc and 12 bpc. >> >> >> >> Note that encoder_control_digx_v5() has proper setup code in place >> >> and is used, e.g., by DCE-11.2, but this code wasn't used for deep >> >> color setup due to the missing cntl.color_depth setup in the calling >> >> function for HDMI. >> >> >> >> set_pixel_clock_v5() - Missing setup code wrt. classic amdgpu/radeon >> >> kms. Added here, but untested due to lack of hw. >> >> >> >> set_pixel_clock_v6() - Missing setup code added. Successfully tested >> >> on AMD mullins DCE-8.3. This fixes corrupted display output at HDMI >> >> deep color output with 10 bpc or 12 bpc. >> >> >> >> Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)") >> >> >> >> Signed-off-by: Mario Kleiner >> >> Cc: Harry Wentland >> > >> > These make sense. I've applied the series. I'll let the display guys >> > gauge the other points in your cover letter. >> > >> > Alex >> >> I don't have any concerns with this patch. >> >> Even though it's already applied feel free to have my: >> >> Reviewed-by: Nicholas Kazlauskas >> >> Regards, >> Nicholas Kazlauskas >> >> > >> > >> >> --- >> >> .../drm/amd/display/dc/bios/command_table.c | 61 >> +++++++++++++++++++ >> >> .../drm/amd/display/dc/dce/dce_clock_source.c | 14 +++++ >> >> .../amd/display/dc/dce/dce_stream_encoder.c | 1 + >> >> 3 files changed, 76 insertions(+) >> >> >> >> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c >> b/drivers/gpu/drm/amd/display/dc/bios/command_table.c >> >> index 070459e3e407..afc10b954ffa 100644 >> >> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c >> >> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c >> >> @@ -245,6 +245,23 @@ static enum bp_result encoder_control_digx_v3( >> >> cntl->enable_dp_audio); >> >> params.ucLaneNum =3D (uint8_t)(cntl->lanes_number); >> >> >> >> + switch (cntl->color_depth) { >> >> + case COLOR_DEPTH_888: >> >> + params.ucBitPerColor =3D PANEL_8BIT_PER_COLOR; >> >> + break; >> >> + case COLOR_DEPTH_101010: >> >> + params.ucBitPerColor =3D PANEL_10BIT_PER_COLOR; >> >> + break; >> >> + case COLOR_DEPTH_121212: >> >> + params.ucBitPerColor =3D PANEL_12BIT_PER_COLOR; >> >> + break; >> >> + case COLOR_DEPTH_161616: >> >> + params.ucBitPerColor =3D PANEL_16BIT_PER_COLOR; >> >> + break; >> >> + default: >> >> + break; >> >> + } >> >> + >> >> if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params)) >> >> result =3D BP_RESULT_OK; >> >> >> >> @@ -274,6 +291,23 @@ static enum bp_result encoder_control_digx_v4( >> >> cntl->enable_dp_audio)); >> >> params.ucLaneNum =3D (uint8_t)(cntl->lanes_number); >> >> >> >> + switch (cntl->color_depth) { >> >> + case COLOR_DEPTH_888: >> >> + params.ucBitPerColor =3D PANEL_8BIT_PER_COLOR; >> >> + break; >> >> + case COLOR_DEPTH_101010: >> >> + params.ucBitPerColor =3D PANEL_10BIT_PER_COLOR; >> >> + break; >> >> + case COLOR_DEPTH_121212: >> >> + params.ucBitPerColor =3D PANEL_12BIT_PER_COLOR; >> >> + break; >> >> + case COLOR_DEPTH_161616: >> >> + params.ucBitPerColor =3D PANEL_16BIT_PER_COLOR; >> >> + break; >> >> + default: >> >> + break; >> >> + } >> >> + >> >> if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params)) >> >> result =3D BP_RESULT_OK; >> >> >> >> @@ -1057,6 +1091,19 @@ static enum bp_result set_pixel_clock_v5( >> >> * driver choose program it itself, i.e. here we >> program it >> >> * to 888 by default. >> >> */ >> >> + if (bp_params->signal_type =3D=3D SIGNAL_TYPE_HDMI_TY= PE_A) >> >> + switch (bp_params->color_depth) { >> >> + case TRANSMITTER_COLOR_DEPTH_30: >> >> + /* yes this is correct, the atom >> define is wrong */ >> >> + clk.sPCLKInput.ucMiscInfo |=3D >> PIXEL_CLOCK_V5_MISC_HDMI_32BPP; >> >> + break; >> >> + case TRANSMITTER_COLOR_DEPTH_36: >> >> + /* yes this is correct, the atom >> define is wrong */ >> >> + clk.sPCLKInput.ucMiscInfo |=3D >> PIXEL_CLOCK_V5_MISC_HDMI_30BPP; >> >> + break; >> >> + default: >> >> + break; >> >> + } >> >> >> >> if (EXEC_BIOS_CMD_TABLE(SetPixelClock, clk)) >> >> result =3D BP_RESULT_OK; >> >> @@ -1135,6 +1182,20 @@ static enum bp_result set_pixel_clock_v6( >> >> * driver choose program it itself, i.e. here we pas= s >> required >> >> * target rate that includes deep color. >> >> */ >> >> + if (bp_params->signal_type =3D=3D SIGNAL_TYPE_HDMI_TY= PE_A) >> >> + switch (bp_params->color_depth) { >> >> + case TRANSMITTER_COLOR_DEPTH_30: >> >> + clk.sPCLKInput.ucMiscInfo |=3D >> PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6; >> >> + break; >> >> + case TRANSMITTER_COLOR_DEPTH_36: >> >> + clk.sPCLKInput.ucMiscInfo |=3D >> PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6; >> >> + break; >> >> + case TRANSMITTER_COLOR_DEPTH_48: >> >> + clk.sPCLKInput.ucMiscInfo |=3D >> PIXEL_CLOCK_V6_MISC_HDMI_48BPP; >> >> + break; >> >> + default: >> >> + break; >> >> + } >> >> >> >> if (EXEC_BIOS_CMD_TABLE(SetPixelClock, clk)) >> >> result =3D BP_RESULT_OK; >> >> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c >> b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c >> >> index fb733f573715..466f8f5803c9 100644 >> >> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c >> >> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c >> >> @@ -871,6 +871,20 @@ static bool dce110_program_pix_clk( >> >> bp_pc_params.flags.SET_EXTERNAL_REF_DIV_SRC =3D >> >> >> pll_settings->use_external_clk; >> >> >> >> + switch (pix_clk_params->color_depth) { >> >> + case COLOR_DEPTH_101010: >> >> + bp_pc_params.color_depth =3D TRANSMITTER_COLOR_DEPTH_= 30; >> >> + break; >> >> + case COLOR_DEPTH_121212: >> >> + bp_pc_params.color_depth =3D TRANSMITTER_COLOR_DEPTH_= 36; >> >> + break; >> >> + case COLOR_DEPTH_161616: >> >> + bp_pc_params.color_depth =3D TRANSMITTER_COLOR_DEPTH_= 48; >> >> + break; >> >> + default: >> >> + break; >> >> + } >> >> + >> >> if (clk_src->bios->funcs->set_pixel_clock( >> >> clk_src->bios, &bp_pc_params) !=3D BP_RESULT= _OK) >> >> return false; >> >> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c >> b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c >> >> index ada57f745fd7..19e380e0a330 100644 >> >> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c >> >> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c >> >> @@ -564,6 +564,7 @@ static void >> dce110_stream_encoder_hdmi_set_stream_attribute( >> >> cntl.enable_dp_audio =3D enable_audio; >> >> cntl.pixel_clock =3D actual_pix_clk_khz; >> >> cntl.lanes_number =3D LANE_COUNT_FOUR; >> >> + cntl.color_depth =3D crtc_timing->display_color_depth; >> >> >> >> if (enc110->base.bp->funcs->encoder_control( >> >> enc110->base.bp, &cntl) !=3D BP_RESULT_OK) >> >> -- >> >> 2.25.1 >> >> >> >> _______________________________________________ >> >> dri-devel mailing list >> >> dri-devel@lists.freedesktop.org >> >> >> https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Flist= s.freedesktop.org%2Fmailman%2Flistinfo%2Fdri-devel&data=3D04%7C01%7Cnic= holas.kazlauskas%40amd.com%7C598b2b5e841940b8c27708d8c15aa80d%7C3dd8961fe48= 84e608e11a82d994e183d%7C0%7C0%7C637471942408643835%7CUnknown%7CTWFpbGZsb3d8= eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&a= mp;sdata=3Db9C3Xi%2F2RmNsGyGUN5oBF8U%2BuGyt2w4jUZ2dK8NM4AY%3D&reserved= =3D0 >> > _______________________________________________ >> > dri-devel mailing list >> > dri-devel@lists.freedesktop.org >> > >> https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Flist= s.freedesktop.org%2Fmailman%2Flistinfo%2Fdri-devel&data=3D04%7C01%7Cnic= holas.kazlauskas%40amd.com%7C598b2b5e841940b8c27708d8c15aa80d%7C3dd8961fe48= 84e608e11a82d994e183d%7C0%7C0%7C637471942408643835%7CUnknown%7CTWFpbGZsb3d8= eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&a= mp;sdata=3Db9C3Xi%2F2RmNsGyGUN5oBF8U%2BuGyt2w4jUZ2dK8NM4AY%3D&reserved= =3D0 >> > >> >> --0000000000001a038c05bb01c899 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Ping. Any bit of info appreciated wrt. the DCE-11.2+ situa= tion.
-mario

On Mon, Jan 25, 2021 at 8:24 PM Mario Kleiner <mario.kleiner.de@gmail.com&g= t; wrote:
Thanks Alex and Nicholas! Brings quite a bit of extra shiny= to those older asics :)

Nicholas, any thoughts on= my cover-letter wrt. why a similar patch (that I wrote and tested to no go= od or bad effect) not seem to be needed on DCN, and probably not DCE-11.2+ = either? Is what is left in DC for those asic's just dead code? My Atomb= ios disassembly sort of pointed into that direction, but reading disassembl= y is not easy on the brain, and my brain was getting quite mushy towards th= e end of digging through all the code. So some official statement would add= peace of mind on my side. Is there a certain DCE version at which your tea= m starts validating output precision / HDR etc. on hw?

Thanks,
-mario


On Mon, Jan 25, 2021= at 8:16 PM Kazlauskas, Nicholas <nicholas.kazlauskas@amd.com> wrote:
On 2021-01-25 12:57 p= .m., Alex Deucher wrote:
> On Thu, Jan 21, 2021 at 1:17 AM Mario Kleiner
> <ma= rio.kleiner.de@gmail.com> wrote:
>>
>> This fixes corrupted display output in HDMI deep color
>> 10/12 bpc mode at least as observed on AMD Mullins, DCE-8.3.
>>
>> It will hopefully also provide fixes for other DCE's up to
>> DCE-11, assuming those will need similar fixes, but i could
>> not test that for HDMI due to lack of suitable hw, so viewer
>> discretion is advised.
>>
>> dce110_stream_encoder_hdmi_set_stream_attribute() is used for
>> HDMI setup on all DCE's and is missing color_depth assignment.=
>>
>> dce110_program_pix_clk() is used for pixel clock setup on HDMI
>> for DCE 6-11, and is missing color_depth assignment.
>>
>> Additionally some of the underlying Atombios specific encoder
>> and pixelclock setup functions are missing code which is in
>> the classic amdgpu kms modesetting path and the in the radeon
>> kms driver for DCE6/DCE8.
>>
>> encoder_control_digx_v3() - Was missing setup code wrt. amdgpu
>> and radeon kms classic drivers. Added here, but untested due to >> lack of suitable test hw.
>>
>> encoder_control_digx_v4() - Added missing setup code.
>> Successfully tested on AMD mullins / DCE-8.3 with HDMI deep color<= br> >> output at 10 bpc and 12 bpc.
>>
>> Note that encoder_control_digx_v5() has proper setup code in place=
>> and is used, e.g., by DCE-11.2, but this code wasn't used for = deep
>> color setup due to the missing cntl.color_depth setup in the calli= ng
>> function for HDMI.
>>
>> set_pixel_clock_v5() - Missing setup code wrt. classic amdgpu/rade= on
>> kms. Added here, but untested due to lack of hw.
>>
>> set_pixel_clock_v6() - Missing setup code added. Successfully test= ed
>> on AMD mullins DCE-8.3. This fixes corrupted display output at HDM= I
>> deep color output with 10 bpc or 12 bpc.
>>
>> Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)&= quot;)
>>
>> Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
>> Cc: Harry Wentland <harry.wentland@amd.com>
>
> These make sense. I've applied the series.=C2=A0 I'll let the = display guys
> gauge the other points in your cover letter.
>
> Alex

I don't have any concerns with this patch.

Even though it's already applied feel free to have my:

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>

Regards,
Nicholas Kazlauskas

>
>
>> ---
>>=C2=A0 =C2=A0.../drm/amd/display/dc/bios/command_table.c=C2=A0 =C2= =A0| 61 +++++++++++++++++++
>>=C2=A0 =C2=A0.../drm/amd/display/dc/dce/dce_clock_source.c | 14 +++= ++
>>=C2=A0 =C2=A0.../amd/display/dc/dce/dce_stream_encoder.c=C2=A0 =C2= =A0|=C2=A0 1 +
>>=C2=A0 =C2=A03 files changed, 76 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b= /drivers/gpu/drm/amd/display/dc/bios/command_table.c
>> index 070459e3e407..afc10b954ffa 100644
>> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
>> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
>> @@ -245,6 +245,23 @@ static enum bp_result encoder_control_digx_v3= (
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 cntl->enable_dp_audio);
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 params.ucLaneNum =3D (uint8_t)(c= ntl->lanes_number);
>>
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0switch (cntl->color_depth) {
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0case COLOR_DEPTH_888:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0params.ucB= itPerColor =3D PANEL_8BIT_PER_COLOR;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0case COLOR_DEPTH_101010:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0params.ucB= itPerColor =3D PANEL_10BIT_PER_COLOR;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0case COLOR_DEPTH_121212:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0params.ucB= itPerColor =3D PANEL_12BIT_PER_COLOR;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0case COLOR_DEPTH_161616:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0params.ucB= itPerColor =3D PANEL_16BIT_PER_COLOR;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0default:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>> +
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (EXEC_BIOS_CMD_TABLE(DIGxEnco= derControl, params))
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 resu= lt =3D BP_RESULT_OK;
>>
>> @@ -274,6 +291,23 @@ static enum bp_result encoder_control_digx_v4= (
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 cntl->enable_dp_audio));
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 params.ucLaneNum =3D (uint8_t)(c= ntl->lanes_number);
>>
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0switch (cntl->color_depth) {
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0case COLOR_DEPTH_888:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0params.ucB= itPerColor =3D PANEL_8BIT_PER_COLOR;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0case COLOR_DEPTH_101010:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0params.ucB= itPerColor =3D PANEL_10BIT_PER_COLOR;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0case COLOR_DEPTH_121212:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0params.ucB= itPerColor =3D PANEL_12BIT_PER_COLOR;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0case COLOR_DEPTH_161616:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0params.ucB= itPerColor =3D PANEL_16BIT_PER_COLOR;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0default:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>> +
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (EXEC_BIOS_CMD_TABLE(DIGxEnco= derControl, params))
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 resu= lt =3D BP_RESULT_OK;
>>
>> @@ -1057,6 +1091,19 @@ static enum bp_result set_pixel_clock_v5( >>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0* driver choose program it itself, i.e. here we program it
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0* to 888 by default.
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0*/
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (bp_par= ams->signal_type =3D=3D SIGNAL_TYPE_HDMI_TYPE_A)
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0switch (bp_params->color_depth) {
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0case TRANSMITTER_COLOR_DEPTH_30:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* yes this is correct, the= atom define is wrong */
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0clk.sPCLKInput.ucMiscInfo |= =3D PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0case TRANSMITTER_COLOR_DEPTH_36:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* yes this is correct, the= atom define is wrong */
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0clk.sPCLKInput.ucMiscInfo |= =3D PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0default:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0}
>>
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (= EXEC_BIOS_CMD_TABLE(SetPixelClock, clk))
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 result =3D BP_RESULT_OK;
>> @@ -1135,6 +1182,20 @@ static enum bp_result set_pixel_clock_v6( >>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0* driver choose program it itself, i.e. here we pass required
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0* target rate that includes deep color.
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0*/
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (bp_par= ams->signal_type =3D=3D SIGNAL_TYPE_HDMI_TYPE_A)
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0switch (bp_params->color_depth) {
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0case TRANSMITTER_COLOR_DEPTH_30:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0clk.sPCLKInput.ucMiscInfo |= =3D PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0case TRANSMITTER_COLOR_DEPTH_36:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0clk.sPCLKInput.ucMiscInfo |= =3D PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0case TRANSMITTER_COLOR_DEPTH_48:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0clk.sPCLKInput.ucMiscInfo |= =3D PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0default:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0}
>>
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (= EXEC_BIOS_CMD_TABLE(SetPixelClock, clk))
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 result =3D BP_RESULT_OK;
>> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c= b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
>> index fb733f573715..466f8f5803c9 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
>> @@ -871,6 +871,20 @@ static bool dce110_program_pix_clk(
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bp_pc_params.flags.SET_EXTERNAL_= REF_DIV_SRC =3D
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 pll_settings->use_external_clk;
>>
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0switch (pix_clk_params->color_depth= ) {
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0case COLOR_DEPTH_101010:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0bp_pc_para= ms.color_depth =3D TRANSMITTER_COLOR_DEPTH_30;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0case COLOR_DEPTH_121212:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0bp_pc_para= ms.color_depth =3D TRANSMITTER_COLOR_DEPTH_36;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0case COLOR_DEPTH_161616:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0bp_pc_para= ms.color_depth =3D TRANSMITTER_COLOR_DEPTH_48;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0default:
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>> +
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (clk_src->bios->funcs-&= gt;set_pixel_clock(
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 clk_src->bios, &bp_pc_params) !=3D BP_RESUL= T_OK)
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 retu= rn false;
>> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder= .c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
>> index ada57f745fd7..19e380e0a330 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
>> @@ -564,6 +564,7 @@ static void dce110_stream_encoder_hdmi_set_str= eam_attribute(
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cntl.enable_dp_audio =3D enable_= audio;
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cntl.pixel_clock =3D actual_pix_= clk_khz;
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cntl.lanes_number =3D LANE_COUNT= _FOUR;
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0cntl.color_depth =3D crtc_timing->d= isplay_color_depth;
>>
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (enc110->base.bp->funcs= ->encoder_control(
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 enc110->base.bp, &cntl) !=3D BP_RESULT_OK)<= br> >> --
>> 2.25.1
>>
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>> dri-devel@lists.freedesktop.org
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>

--0000000000001a038c05bb01c899-- --===============0671984977== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx --===============0671984977==--