From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5FA57C433EF for ; Sun, 19 Jun 2022 14:47:55 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8675884239; Sun, 19 Jun 2022 16:47:53 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="kmbdjo+X"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id BC0CC83F6B; Sun, 19 Jun 2022 16:47:52 +0200 (CEST) Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D510C84239 for ; Sun, 19 Jun 2022 16:47:48 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=heiko.thiery@gmail.com Received: by mail-wr1-x42f.google.com with SMTP id q9so11446609wrd.8 for ; Sun, 19 Jun 2022 07:47:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=f3YHs5wJRiy34ElAtWK99smiLI33DGEIUbt8DR1c31U=; b=kmbdjo+XOSd2Gj1P4cruvg07DgdrO4UHRrFG9GeFZ+rff2PbbbHKTotPccz1Nv0W50 tzHWKp+qGJNv7n0lqqVySnMXo+RMO0sFTt7DYgkZTsSD9Aj19BUAmR/YMrltXW8OoDyC aHb5Ms7avUYS6dIkJvF67dKmeRS+4h5aOdrSxB6zrdB7fK4T6zdFXbm+8Tog5T9JDAQc aEynFUg1Z/LjjlrbUbX2cliQF69a/17nJf3w/kZGof95BBdpE2oXUVLaEM1LEliCm1X7 kBckFooOgb97w/mB0pXZ2A/fmY34keuZ1ieQkWQvw8GHbZgClGfymUDalK84EALjYa9G dUkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=f3YHs5wJRiy34ElAtWK99smiLI33DGEIUbt8DR1c31U=; b=CTZsfV8K5/D1/CueIuEPV92AxoTf3HSSCm+vT+lt7F99v2vPSUkKsyB919R+MNTmXb m/2/52OFbVmlyr7i15nNXX4vBRxBiLRIfxjOM51OZmYG9UDzQNwYjV9EsJENO+PPveOS 0SV1SwnS5CAsUXOgRIiat1OycgDdMnlQ/pOTBHgmbupAH4oTyndqzU2zcNOzmqnX5ff/ opZ7MaKQzBcLJ5FP3p5x5nnUtaVDj5vKB8ueDzk09/OmwiOML9RabYYBWcXC/z3x6yfE j8vETc8Yx2FNNmij9z6HFTL2nY0m1HB7BTJ8hgcH+2tz9Croch+JG3sIMgrDnjwNv7l0 Tajw== X-Gm-Message-State: AJIora8QDxINK4odUkLCTUusWtGRbeuijed64QB6rmrt9P4d4BhAQQzi tYnuPUybnzxipzJXbGn5IeHKInmzDdVY1GNG7BM= X-Google-Smtp-Source: AGRyM1vaDkjV7Q4MwLdB0l/RDhyeJeJmAksWnV1mJsMycJfSEXzTQRMQ9Bb9dg/bmztjDuf8WK5mwAy4zxc2JXAieWU= X-Received: by 2002:adf:fa12:0:b0:21a:266c:183a with SMTP id m18-20020adffa12000000b0021a266c183amr18025695wrr.553.1655650068291; Sun, 19 Jun 2022 07:47:48 -0700 (PDT) MIME-Version: 1.0 References: <20220613211005.30871-1-heiko.thiery@gmail.com> In-Reply-To: From: Heiko Thiery Date: Sun, 19 Jun 2022 16:47:36 +0200 Message-ID: Subject: Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support To: Michael Nazzareno Trimarchi Cc: Marek Vasut , U-Boot-Denx , Ying-Chun Liu , Peng Fan , Fabio Estevam , Marcel Ziswiler , Tim Harvey , Sean Anderson , =?UTF-8?Q?Thomas_Sch=C3=A4fer?= , Stefano Babic , Fabio Estevam Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Hi, Am So., 19. Juni 2022 um 16:40 Uhr schrieb Michael Nazzareno Trimarchi : > > Hi Heiko > > On Sun, Jun 19, 2022 at 8:12 AM Heiko Thiery wro= te: > > > > Hi, > > > > Am So., 19. Juni 2022 um 07:59 Uhr schrieb Michael Nazzareno Trimarchi > > : > > > > > > Hi > > > > > > Il sab 18 giu 2022, 23:56 Heiko Thiery ha sc= ritto: > > >> > > >> Hi Michael, Hi Marek, > > >> > > >> Am Mi., 15. Juni 2022 um 08:43 Uhr schrieb Michael Nazzareno Trimarc= hi > > >> : > > >> > > > >> > Hi Heiko > > >> > > > >> > On Wed, Jun 15, 2022 at 8:23 AM Heiko Thiery wrote: > > >> > > > > >> > > Hi Marek, > > >> > > > > >> > > [SNIP] > > >> > > > > >> > > > > diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freesc= ale/imx8mn_evk/spl.c > > >> > > > > index 14cb51368f..0d9909a662 100644 > > >> > > > > --- a/board/freescale/imx8mn_evk/spl.c > > >> > > > > +++ b/board/freescale/imx8mn_evk/spl.c > > >> > > > > @@ -83,6 +83,15 @@ int power_init_board(void) > > >> > > > > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE > > >> > > > > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode *= / > > >> > > > > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); > > >> > > > > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK) > > >> > > > > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */ > > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); > > >> > > > > + > > >> > > > > + /* Disable the BUCK2 */ > > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48); > > >> > > > > + > > >> > > > > + /* Set NVCC_DRAM to 1.35v */ > > >> > > > > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E); > > >> > > > > #else > > >> > > > > > >> > > > All this part is not done by the spl pmic driver? > > >> > > > > >> > > I saw that you added the PCA9450 driver. Do you know if this > > >> > > initialization can be done by the driver when CONFIG_SPL_DM_REGU= LATOR > > >> > > is enabled? If I see this correctly, it can't be done. Is that > > >> > > correct? > > >> > > > >> > +&i2c1 { > > >> > + u-boot,dm-spl; > > >> > +}; > > >> > + > > >> > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { > > >> > + u-boot,dm-spl; > > >> > +}; > > >> > + > > >> > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { > > >> > + u-boot,dm-spl; > > >> > +}; > > >> > + > > >> > +&pinctrl_i2c1 { > > >> > + u-boot,dm-spl; > > >> > +}; > > >> > + > > >> > +&pinctrl_pmic { > > >> > + u-boot,dm-spl; > > >> > +}; > > >> > + > > >> > > > >> > Maybe something like this should work. Now question is about shoul= d be > > >> > done in pre-reloc or not > > >> > > >> It took me a little while to understand what was meant by this. In t= he > > >> meantime I could > > >> change the PMIC/Regulator initialization to DT/DM and can make the s= etting so. > > >> What is not clear to me yet is at which point this should be done > > >> (regulators_enable_boot_on()). Currently I do it in the board/spl > > >> specific board_init_f(). > > >> > > >> Do any of you have any advice here? > > > > > > > > > After having a discussion with you, i found that maybe i have some pr= oblem and some of the setting should be done before ddr inizialization. I w= ill take a look on it on afternoon. I know marek was working on some way to= probe driver during binding and we need even to be sure that this can happ= en before memory training. > > > > > > > Currently I added it in board_init_f() right before spl_dram_init() > > [1] and it works. I also tried to put it in power_init_board() [2] but > > this does not work. > > > > [1] https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/i= mx8mn_evk/spl.c#L162 > > [2] https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/i= mx8mn_evk/spl.c#L62 > > Does it work if you mark pre-reoloc, pmic, i2c, and pinctrl? I added on all nodes the u-boot,dm-pre-reloc but this does not help when trying to do the init in power_init_board(). > > Michael > > > > > -- > > Heiko > > > > > Michael > > >> > > >> > > >> Thanks > > >> -- > > >> Heiko > > >> > > >> > Michael > > >> > > > > >> > > -- > > >> > > Heiko > > >> > > > >> > > > >> > > > >> > -- > > >> > Michael Nazzareno Trimarchi > > >> > Co-Founder & Chief Executive Officer > > >> > M. +39 347 913 2170 > > >> > michael@amarulasolutions.com > > >> > __________________________________ > > >> > > > >> > Amarula Solutions BV > > >> > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL > > >> > T. +31 (0)85 111 9172 > > >> > info@amarulasolutions.com > > >> > www.amarulasolutions.com > > > > -- > Michael Nazzareno Trimarchi > Co-Founder & Chief Executive Officer > M. +39 347 913 2170 > michael@amarulasolutions.com > __________________________________ > > Amarula Solutions BV > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL > T. +31 (0)85 111 9172 > info@amarulasolutions.com > www.amarulasolutions.com