From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB568C43334 for ; Sun, 19 Jun 2022 06:12:10 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D96F984280; Sun, 19 Jun 2022 08:12:08 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="XC6h1E97"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id A61968433F; Sun, 19 Jun 2022 08:12:07 +0200 (CEST) Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1C55183EA6 for ; Sun, 19 Jun 2022 08:12:05 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=heiko.thiery@gmail.com Received: by mail-wm1-x335.google.com with SMTP id m32-20020a05600c3b2000b0039756bb41f2so4206618wms.3 for ; Sat, 18 Jun 2022 23:12:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=p1azNORnvjB1LVdQ5k+5V3mymzpXAPTY7qpRGIu4WV0=; b=XC6h1E97rQgLwyiOskqQzJr92idr9DMpGl5qEfARpUmnGVdxuhWPmC21lYu/WlucAK Fpgur9nspXCoHyO8lmjnAZcyCwPcDcy+6yka0+ce2J9f5PL3BUD5fn5O3/4WbCyWVCD6 NYsWJ+GTmsJJaBsmtDTlURmq6wOSEwhrSCN8PFPLdsySIQAhfHAAv0142UPTgIJ7TvEF 1lqC89ZBpK+h3eTPCKDVeY06/R8qA6DnyQ1EiNG0ixIp5QsHFV4g6SEngR0V2luGrx5O j27XImxUH9kHN/VQ2b13P6+Mu4ehDJ6L4S4fCLT64l/hSTUc3QaTmWUN2LUG/OybydD4 eyFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=p1azNORnvjB1LVdQ5k+5V3mymzpXAPTY7qpRGIu4WV0=; b=ozr4n2CdGIYdxzlguBD2kDT3pQo1U+fFxQSHTR7MvuIgJ7QdYpKb1RtCH6yBHg5ezG KUXiBn+hDOQHT6iGRDHfJvis0L7/srcVmrXSOoYy5nOzEH47FSz4+4q6tavjawAR4tJl x6JvJxtHSYNo3eHbrPGbEuN66uQTh7mK7J6So2SeAX9xfcHxN1iBtDUP5sptMMy4pj20 5VfW2fVNAVIk3moObT84e4f92HR9EzSKIRF5LZYiR0zUIgdgLl/YfDJW7Ln0BD0vDiX/ WVG41qv6KQ+RsilIKHHGe/3wG4h7m8+L9RGXpmLqTZTHd8s1BVBqDav66PknYM/mAGtd uGhg== X-Gm-Message-State: AJIora/+1UDY1N66J57vBnFFnqvvQtDACBTwJL6svi2hexru0PYcvoep rXB2ujS7KA+1rK9z8GSwiV64VcFmaEbLyrfuBOk= X-Google-Smtp-Source: AGRyM1uMbeRgObqdhxSXwglKhuH8xHtkNKkg+7czdeh/EPPP29R/wPluwN0VtfQMCAiK75MOrt909A9O7DmjoUO/bG0= X-Received: by 2002:a05:600c:3485:b0:39c:7db5:f0f7 with SMTP id a5-20020a05600c348500b0039c7db5f0f7mr18399091wmq.8.1655619124542; Sat, 18 Jun 2022 23:12:04 -0700 (PDT) MIME-Version: 1.0 References: <20220613211005.30871-1-heiko.thiery@gmail.com> In-Reply-To: From: Heiko Thiery Date: Sun, 19 Jun 2022 08:11:53 +0200 Message-ID: Subject: Re: [PATCH v4] imx: add i.MX8MN DDR3L evk board support To: Michael Nazzareno Trimarchi Cc: Marek Vasut , U-Boot-Denx , Ying-Chun Liu , Peng Fan , Fabio Estevam , Marcel Ziswiler , Tim Harvey , Sean Anderson , =?UTF-8?Q?Thomas_Sch=C3=A4fer?= , Stefano Babic , Fabio Estevam Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Hi, Am So., 19. Juni 2022 um 07:59 Uhr schrieb Michael Nazzareno Trimarchi : > > Hi > > Il sab 18 giu 2022, 23:56 Heiko Thiery ha scritt= o: >> >> Hi Michael, Hi Marek, >> >> Am Mi., 15. Juni 2022 um 08:43 Uhr schrieb Michael Nazzareno Trimarchi >> : >> > >> > Hi Heiko >> > >> > On Wed, Jun 15, 2022 at 8:23 AM Heiko Thiery = wrote: >> > > >> > > Hi Marek, >> > > >> > > [SNIP] >> > > >> > > > > diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/= imx8mn_evk/spl.c >> > > > > index 14cb51368f..0d9909a662 100644 >> > > > > --- a/board/freescale/imx8mn_evk/spl.c >> > > > > +++ b/board/freescale/imx8mn_evk/spl.c >> > > > > @@ -83,6 +83,15 @@ int power_init_board(void) >> > > > > #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE >> > > > > /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */ >> > > > > pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); >> > > > > +#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_EVK) >> > > > > + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */ >> > > > > + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); >> > > > > + >> > > > > + /* Disable the BUCK2 */ >> > > > > + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48); >> > > > > + >> > > > > + /* Set NVCC_DRAM to 1.35v */ >> > > > > + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E); >> > > > > #else >> > > > >> > > > All this part is not done by the spl pmic driver? >> > > >> > > I saw that you added the PCA9450 driver. Do you know if this >> > > initialization can be done by the driver when CONFIG_SPL_DM_REGULATO= R >> > > is enabled? If I see this correctly, it can't be done. Is that >> > > correct? >> > >> > +&i2c1 { >> > + u-boot,dm-spl; >> > +}; >> > + >> > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { >> > + u-boot,dm-spl; >> > +}; >> > + >> > +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { >> > + u-boot,dm-spl; >> > +}; >> > + >> > +&pinctrl_i2c1 { >> > + u-boot,dm-spl; >> > +}; >> > + >> > +&pinctrl_pmic { >> > + u-boot,dm-spl; >> > +}; >> > + >> > >> > Maybe something like this should work. Now question is about should be >> > done in pre-reloc or not >> >> It took me a little while to understand what was meant by this. In the >> meantime I could >> change the PMIC/Regulator initialization to DT/DM and can make the setti= ng so. >> What is not clear to me yet is at which point this should be done >> (regulators_enable_boot_on()). Currently I do it in the board/spl >> specific board_init_f(). >> >> Do any of you have any advice here? > > > After having a discussion with you, i found that maybe i have some proble= m and some of the setting should be done before ddr inizialization. I will = take a look on it on afternoon. I know marek was working on some way to pro= be driver during binding and we need even to be sure that this can happen b= efore memory training. > Currently I added it in board_init_f() right before spl_dram_init() [1] and it works. I also tried to put it in power_init_board() [2] but this does not work. [1] https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8m= n_evk/spl.c#L162 [2] https://elixir.bootlin.com/u-boot/v2022.04/source/board/freescale/imx8m= n_evk/spl.c#L62 -- Heiko > Michael >> >> >> Thanks >> -- >> Heiko >> >> > Michael >> > > >> > > -- >> > > Heiko >> > >> > >> > >> > -- >> > Michael Nazzareno Trimarchi >> > Co-Founder & Chief Executive Officer >> > M. +39 347 913 2170 >> > michael@amarulasolutions.com >> > __________________________________ >> > >> > Amarula Solutions BV >> > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL >> > T. +31 (0)85 111 9172 >> > info@amarulasolutions.com >> > www.amarulasolutions.com