From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F05F8C43461 for ; Fri, 4 Sep 2020 16:47:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B12CB2064E for ; Fri, 4 Sep 2020 16:47:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="EgsDNr8j" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726733AbgIDQrA (ORCPT ); Fri, 4 Sep 2020 12:47:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53362 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726063AbgIDQq7 (ORCPT ); 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charset="UTF-8" Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Fri, Sep 4, 2020 at 2:11 AM Joerg Roedel wrote: > > On Mon, Aug 17, 2020 at 03:01:25PM -0700, Rob Clark wrote: > > Jordan Crouse (12): > > iommu/arm-smmu: Pass io-pgtable config to implementation specific > > function > > iommu/arm-smmu: Add support for split pagetables > > iommu/arm-smmu: Prepare for the adreno-smmu implementation > > iommu/arm-smmu-qcom: Add implementation for the adreno GPU SMMU > > dt-bindings: arm-smmu: Add compatible string for Adreno GPU SMMU > > drm/msm: Add a context pointer to the submitqueue > > drm/msm: Drop context arg to gpu->submit() > > drm/msm: Set the global virtual address range from the IOMMU domain > > drm/msm: Add support to create a local pagetable > > drm/msm: Add support for private address space instances > > drm/msm/a6xx: Add support for per-instance pagetables > > arm: dts: qcom: sm845: Set the compatible string for the GPU SMMU > > > > Rob Clark (8): > > drm/msm: remove dangling submitqueue references > > iommu: add private interface for adreno-smmu > > drm/msm/gpu: add dev_to_gpu() helper > > drm/msm: set adreno_smmu as gpu's drvdata > > iommu/arm-smmu: constify some helpers > > arm: dts: qcom: sc7180: Set the compatible string for the GPU SMMU > > iommu/arm-smmu: add a way for implementations to influence SCTLR > > drm/msm: show process names in gem_describe > > Can the DRM parts be merged independently from the IOMMU parts or does > this need to be queued together? If it needs to be together I defer the > decission to Will through which tree this should go. > Hi, v16 of this series re-ordered the patches and has some notes at the top of the cover letter[1] about a potential way to land it.. tl;dr: the drm parts can and adreno-smmu-priv.h can go independently of iommu. And the first four iommu patches can go in independently of drm. But the last two iommu patches have a dependency on the drm patches. Note that I'll send one more revision of the series shortly (I have a small fixup for one of the drm patches for an issue found in testing, and Bjorn had some suggestions about "iommu/arm-smmu: Prepare for the adreno-smmu implementation" that I need to look at. BR, -R [1] https://lkml.org/lkml/2020/9/1/1469 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.5 required=3.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4160C2BC84 for ; Fri, 4 Sep 2020 16:47:03 +0000 (UTC) Received: from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 75B032064E for ; Fri, 4 Sep 2020 16:47:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="EgsDNr8j" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 75B032064E Authentication-Results: mail.kernel.org; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Fri, Sep 4, 2020 at 2:11 AM Joerg Roedel wrote: > > On Mon, Aug 17, 2020 at 03:01:25PM -0700, Rob Clark wrote: > > Jordan Crouse (12): > > iommu/arm-smmu: Pass io-pgtable config to implementation specific > > function > > iommu/arm-smmu: Add support for split pagetables > > iommu/arm-smmu: Prepare for the adreno-smmu implementation > > iommu/arm-smmu-qcom: Add implementation for the adreno GPU SMMU > > dt-bindings: arm-smmu: Add compatible string for Adreno GPU SMMU > > drm/msm: Add a context pointer to the submitqueue > > drm/msm: Drop context arg to gpu->submit() > > drm/msm: Set the global virtual address range from the IOMMU domain > > drm/msm: Add support to create a local pagetable > > drm/msm: Add support for private address space instances > > drm/msm/a6xx: Add support for per-instance pagetables > > arm: dts: qcom: sm845: Set the compatible string for the GPU SMMU > > > > Rob Clark (8): > > drm/msm: remove dangling submitqueue references > > iommu: add private interface for adreno-smmu > > drm/msm/gpu: add dev_to_gpu() helper > > drm/msm: set adreno_smmu as gpu's drvdata > > iommu/arm-smmu: constify some helpers > > arm: dts: qcom: sc7180: Set the compatible string for the GPU SMMU > > iommu/arm-smmu: add a way for implementations to influence SCTLR > > drm/msm: show process names in gem_describe > > Can the DRM parts be merged independently from the IOMMU parts or does > this need to be queued together? If it needs to be together I defer the > decission to Will through which tree this should go. > Hi, v16 of this series re-ordered the patches and has some notes at the top of the cover letter[1] about a potential way to land it.. tl;dr: the drm parts can and adreno-smmu-priv.h can go independently of iommu. And the first four iommu patches can go in independently of drm. But the last two iommu patches have a dependency on the drm patches. Note that I'll send one more revision of the series shortly (I have a small fixup for one of the drm patches for an issue found in testing, and Bjorn had some suggestions about "iommu/arm-smmu: Prepare for the adreno-smmu implementation" that I need to look at. BR, -R [1] https://lkml.org/lkml/2020/9/1/1469 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.7 required=3.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D32FFC433E2 for ; Fri, 4 Sep 2020 16:48:23 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9271E2064E for ; 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Fri, 04 Sep 2020 09:46:58 -0700 (PDT) MIME-Version: 1.0 References: <20200817220238.603465-1-robdclark@gmail.com> <20200904091117.GH6714@8bytes.org> In-Reply-To: <20200904091117.GH6714@8bytes.org> From: Rob Clark Date: Fri, 4 Sep 2020 09:47:45 -0700 Message-ID: Subject: Re: [PATCH 00/20] iommu/arm-smmu + drm/msm: per-process GPU pgtables To: Joerg Roedel X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200904_124704_032294_D195FE6F X-CRM114-Status: GOOD ( 21.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Wambui Karuga , Takashi Iwai , Hanna Hawa , Akhil P Oommen , dri-devel , Bjorn Andersson , Eric Anholt , Thierry Reding , Vivek Gautam , AngeloGioacchino Del Regno , Will Deacon , Emil Velikov , Rob Clark , Sai Prakash Ranjan , Jonathan Marek , Sam Ravnborg , Jon Hunter , Ben Dooks , Sibi Sankar , Thierry Reding , Brian Masney , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Joerg Roedel , linux-arm-msm , Sharat Masetty , Pritesh Raithatha , Stephen Boyd , Nicolin Chen , Jordan Crouse , John Stultz , freedreno , "moderated list:ARM SMMU DRIVERS" , Greg Kroah-Hartman , open list , "list@263.net:IOMMU DRIVERS , Joerg Roedel , " , Shawn Guo , Robin Murphy Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Sep 4, 2020 at 2:11 AM Joerg Roedel wrote: > > On Mon, Aug 17, 2020 at 03:01:25PM -0700, Rob Clark wrote: > > Jordan Crouse (12): > > iommu/arm-smmu: Pass io-pgtable config to implementation specific > > function > > iommu/arm-smmu: Add support for split pagetables > > iommu/arm-smmu: Prepare for the adreno-smmu implementation > > iommu/arm-smmu-qcom: Add implementation for the adreno GPU SMMU > > dt-bindings: arm-smmu: Add compatible string for Adreno GPU SMMU > > drm/msm: Add a context pointer to the submitqueue > > drm/msm: Drop context arg to gpu->submit() > > drm/msm: Set the global virtual address range from the IOMMU domain > > drm/msm: Add support to create a local pagetable > > drm/msm: Add support for private address space instances > > drm/msm/a6xx: Add support for per-instance pagetables > > arm: dts: qcom: sm845: Set the compatible string for the GPU SMMU > > > > Rob Clark (8): > > drm/msm: remove dangling submitqueue references > > iommu: add private interface for adreno-smmu > > drm/msm/gpu: add dev_to_gpu() helper > > drm/msm: set adreno_smmu as gpu's drvdata > > iommu/arm-smmu: constify some helpers > > arm: dts: qcom: sc7180: Set the compatible string for the GPU SMMU > > iommu/arm-smmu: add a way for implementations to influence SCTLR > > drm/msm: show process names in gem_describe > > Can the DRM parts be merged independently from the IOMMU parts or does > this need to be queued together? If it needs to be together I defer the > decission to Will through which tree this should go. > Hi, v16 of this series re-ordered the patches and has some notes at the top of the cover letter[1] about a potential way to land it.. tl;dr: the drm parts can and adreno-smmu-priv.h can go independently of iommu. And the first four iommu patches can go in independently of drm. But the last two iommu patches have a dependency on the drm patches. Note that I'll send one more revision of the series shortly (I have a small fixup for one of the drm patches for an issue found in testing, and Bjorn had some suggestions about "iommu/arm-smmu: Prepare for the adreno-smmu implementation" that I need to look at. BR, -R [1] https://lkml.org/lkml/2020/9/1/1469 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.5 required=3.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5712FC433E2 for ; Fri, 4 Sep 2020 16:47:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 182742064E for ; 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Fri, 04 Sep 2020 09:46:58 -0700 (PDT) MIME-Version: 1.0 References: <20200817220238.603465-1-robdclark@gmail.com> <20200904091117.GH6714@8bytes.org> In-Reply-To: <20200904091117.GH6714@8bytes.org> From: Rob Clark Date: Fri, 4 Sep 2020 09:47:45 -0700 Message-ID: Subject: Re: [PATCH 00/20] iommu/arm-smmu + drm/msm: per-process GPU pgtables To: Joerg Roedel X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Wambui Karuga , Hanna Hawa , Akhil P Oommen , dri-devel , Bjorn Andersson , Thierry Reding , Vivek Gautam , AngeloGioacchino Del Regno , Will Deacon , Emil Velikov , Rob Clark , Sai Prakash Ranjan , Jonathan Marek , Sam Ravnborg , Jon Hunter , Ben Dooks , Sibi Sankar , Thierry Reding , Brian Masney , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Joerg Roedel , linux-arm-msm , Sharat Masetty , Pritesh Raithatha , Stephen Boyd , Nicolin Chen , freedreno , "moderated list:ARM SMMU DRIVERS" , Greg Kroah-Hartman , Krishna Reddy , open list , "list@263.net:IOMMU DRIVERS , Joerg Roedel , " , Robin Murphy Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Fri, Sep 4, 2020 at 2:11 AM Joerg Roedel wrote: > > On Mon, Aug 17, 2020 at 03:01:25PM -0700, Rob Clark wrote: > > Jordan Crouse (12): > > iommu/arm-smmu: Pass io-pgtable config to implementation specific > > function > > iommu/arm-smmu: Add support for split pagetables > > iommu/arm-smmu: Prepare for the adreno-smmu implementation > > iommu/arm-smmu-qcom: Add implementation for the adreno GPU SMMU > > dt-bindings: arm-smmu: Add compatible string for Adreno GPU SMMU > > drm/msm: Add a context pointer to the submitqueue > > drm/msm: Drop context arg to gpu->submit() > > drm/msm: Set the global virtual address range from the IOMMU domain > > drm/msm: Add support to create a local pagetable > > drm/msm: Add support for private address space instances > > drm/msm/a6xx: Add support for per-instance pagetables > > arm: dts: qcom: sm845: Set the compatible string for the GPU SMMU > > > > Rob Clark (8): > > drm/msm: remove dangling submitqueue references > > iommu: add private interface for adreno-smmu > > drm/msm/gpu: add dev_to_gpu() helper > > drm/msm: set adreno_smmu as gpu's drvdata > > iommu/arm-smmu: constify some helpers > > arm: dts: qcom: sc7180: Set the compatible string for the GPU SMMU > > iommu/arm-smmu: add a way for implementations to influence SCTLR > > drm/msm: show process names in gem_describe > > Can the DRM parts be merged independently from the IOMMU parts or does > this need to be queued together? If it needs to be together I defer the > decission to Will through which tree this should go. > Hi, v16 of this series re-ordered the patches and has some notes at the top of the cover letter[1] about a potential way to land it.. tl;dr: the drm parts can and adreno-smmu-priv.h can go independently of iommu. And the first four iommu patches can go in independently of drm. But the last two iommu patches have a dependency on the drm patches. Note that I'll send one more revision of the series shortly (I have a small fixup for one of the drm patches for an issue found in testing, and Bjorn had some suggestions about "iommu/arm-smmu: Prepare for the adreno-smmu implementation" that I need to look at. BR, -R [1] https://lkml.org/lkml/2020/9/1/1469 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel