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charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Neil, On Tue, Feb 12, 2019 at 4:16 PM Neil Armstrong wrote: > > This adds support for the shared USB3 + PCIE PHY found in the > Amlogic G12A SoC Family. > > It supports USB3 Host mode or PCIE 2.0 mode, depending on the layout of > the board. > > Selection is done by the #phy-cells, making the mode static and exclusive. > > Signed-off-by: Neil Armstrong > --- > drivers/phy/amlogic/Kconfig | 12 + > drivers/phy/amlogic/Makefile | 1 + > .../phy/amlogic/phy-meson-g12a-usb3-pcie.c | 414 ++++++++++++++++++ > 3 files changed, 427 insertions(+) > create mode 100644 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c > > diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig > index 78d6e194dce9..7ccb9a756aba 100644 > --- a/drivers/phy/amlogic/Kconfig > +++ b/drivers/phy/amlogic/Kconfig > @@ -48,3 +48,15 @@ config PHY_MESON_G12A_USB2 > Enable this to support the Meson USB2 PHYs found in Meson > G12A SoCs. > If unsure, say N. > + > +config PHY_MESON_G12A_USB3_PCIE > + tristate "Meson G12A USB3+PCIE Combo PHY drivers" nit-pick: s/drivers/driver/ > + default ARCH_MESON > + depends on OF && (ARCH_MESON || COMPILE_TEST) > + depends on USB_SUPPORT > + select GENERIC_PHY > + select REGMAP_MMIO > + help > + Enable this to support the Meson USB3 + PCIE Combi PHY found > + in Meson G12A SoCs. > + If unsure, say N. > diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile > index 7d4d10f5a6b3..fdd008e1b19b 100644 > --- a/drivers/phy/amlogic/Makefile > +++ b/drivers/phy/amlogic/Makefile > @@ -2,3 +2,4 @@ obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o > obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o > obj-$(CONFIG_PHY_MESON_G12A_USB2) += phy-meson-g12a-usb2.o > obj-$(CONFIG_PHY_MESON_GXL_USB3) += phy-meson-gxl-usb3.o > +obj-$(CONFIG_PHY_MESON_G12A_USB3_PCIE) += phy-meson-g12a-usb3-pcie.o > diff --git a/drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c b/drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c > new file mode 100644 > index 000000000000..59eae98928e9 > --- /dev/null > +++ b/drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c > @@ -0,0 +1,414 @@ [...] > +static int phy_g12a_usb3_init(struct phy *phy) > +{ > + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy); > + int data, ret; > + > + /* Switch PHY to USB3 */ > + regmap_update_bits(priv->regmap, PHY_R0, > + PHY_R0_PCIE_USB3_SWITCH, > + PHY_R0_PCIE_USB3_SWITCH); > + > + /* > + * WORKAROUND: There is SSPHY suspend bug due to > + * which USB enumerates > + * in HS mode instead of SS mode. Workaround it by asserting > + * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus > + * mode > + */ > + ret = regmap_update_bits(priv->regmap_cr, 0x102d, BIT(7), BIT(7)); does the datasheet have names for these registers / bits? it if does then it would be great if you could introduce #defines for them > + if (ret) > + return ret; > + > + ret = regmap_update_bits(priv->regmap_cr, 0x1010, 0xff0, 20); > + if (ret) > + return ret; > + > + /* > + * Fix RX Equalization setting as follows > + * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0 > + * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1 > + * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3 > + * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1 > + */ > + ret = regmap_read(priv->regmap_cr, 0x1006, &data); > + if (ret) > + return ret; > + > + data &= ~BIT(6); > + data |= BIT(7); > + data &= ~(0x7 << 8); > + data |= (0x3 << 8); > + data |= (1 << 11); > + ret = regmap_write(priv->regmap_cr, 0x1006, data); > + if (ret) > + return ret; > + > + /* > + * Set EQ and TX launch amplitudes as follows > + * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22 > + * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127 > + * LANE0.TX_OVRD_DRV_LO.EN set to 1. > + */ > + ret = regmap_read(priv->regmap_cr, 0x1002, &data); > + if (ret) > + return ret; > + > + data &= ~0x3f80; > + data |= (0x16 << 7); > + data &= ~0x7f; > + data |= (0x7f | BIT(14)); > + ret = regmap_write(priv->regmap_cr, 0x1002, data); > + if (ret) > + return ret; > + > + /* > + * MPLL_LOOP_CTL.PROP_CNTRL = 8 > + */ why a multi-line comment here? "Switch PHY to USB3" above uses a single-line comment > + ret = regmap_update_bits(priv->regmap_cr, 0x30, 0xf << 4, 8 << 4); > + if (ret) > + return ret; > + > + regmap_update_bits(priv->regmap, PHY_R2, > + PHY_R2_PHY_TX_VBOOST_LVL, > + FIELD_PREP(PHY_R2_PHY_TX_VBOOST_LVL, 0x4)); > + > + regmap_update_bits(priv->regmap, PHY_R1, > + PHY_R1_PHY_LOS_BIAS | PHY_R1_PHY_LOS_LEVEL, > + FIELD_PREP(PHY_R1_PHY_LOS_BIAS, 4) | > + FIELD_PREP(PHY_R1_PHY_LOS_LEVEL, 9)); > + > + return 0; > +} > + > +static int phy_g12a_usb3_pcie_init(struct phy *phy) > +{ > + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy); > + int ret; > + > + ret = reset_control_reset(priv->reset); > + if (ret) > + return ret; > + > + if (priv->mode == PHY_TYPE_USB3) > + return phy_g12a_usb3_init(phy); > + > + /* Power UP PCIE */ > + regmap_update_bits(priv->regmap, PHY_R0, > + PHY_R0_PCIE_POWER_STATE, > + FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c)); do we also need this for USB mode? also do we need to change the PHY_R2 register values (PHY_R2_PHY_TX_VBOOST_LVL for example) for PCIe, for example if the bootloader initialized the PHY in USB3 mode while the board actually exposes a PCIe port? Regards Martin From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [6/8] phy: amlogic: Add Amlogic G12A USB3 + PCIE Combo PHY Driver From: Martin Blumenstingl Message-Id: Date: Sun, 24 Feb 2019 20:40:37 +0100 To: Neil Armstrong Cc: gregkh@linuxfoundation.org, hminas@synopsys.com, balbi@kernel.org, kishon@ti.com, linux-amlogic@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-ID: SGkgTmVpbCwKCk9uIFR1ZSwgRmViIDEyLCAyMDE5IGF0IDQ6MTYgUE0gTmVpbCBBcm1zdHJvbmcg PG5hcm1zdHJvbmdAYmF5bGlicmUuY29tPiB3cm90ZToKPgo+IFRoaXMgYWRkcyBzdXBwb3J0IGZv ciB0aGUgc2hhcmVkIFVTQjMgKyBQQ0lFIFBIWSBmb3VuZCBpbiB0aGUKPiBBbWxvZ2ljIEcxMkEg U29DIEZhbWlseS4KPgo+IEl0IHN1cHBvcnRzIFVTQjMgSG9zdCBtb2RlIG9yIFBDSUUgMi4wIG1v ZGUsIGRlcGVuZGluZyBvbiB0aGUgbGF5b3V0IG9mCj4gdGhlIGJvYXJkLgo+Cj4gU2VsZWN0aW9u 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X-Gm-Message-State: AHQUAuZqoqCG/QJ00y6BVb8oD+2eAE1jFafyFcdijDwAHdq7ru7WKLew wK0hot0b5JH0pdXKd9hRmyukxD5N15tqGztZSX4= X-Google-Smtp-Source: AHgI3IYsoPfO0Zfqmpdy/kVkQl70w8ybav3C9zxzpYyTna3eo9dZmNjtAScxwNiCtFVQktyARcUm1dikJkE7x+bBPlM= X-Received: by 2002:aca:bc0b:: with SMTP id m11mr8694088oif.41.1551037248237; Sun, 24 Feb 2019 11:40:48 -0800 (PST) MIME-Version: 1.0 References: <20190212151413.24632-1-narmstrong@baylibre.com> <20190212151413.24632-7-narmstrong@baylibre.com> In-Reply-To: <20190212151413.24632-7-narmstrong@baylibre.com> From: Martin Blumenstingl Date: Sun, 24 Feb 2019 20:40:37 +0100 Message-ID: Subject: Re: [PATCH 6/8] phy: amlogic: Add Amlogic G12A USB3 + PCIE Combo PHY Driver To: Neil Armstrong X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190224_114050_205525_AEA8C490 X-CRM114-Status: GOOD ( 25.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: balbi@kernel.org, gregkh@linuxfoundation.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, kishon@ti.com, hminas@synopsys.com, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Neil, On Tue, Feb 12, 2019 at 4:16 PM Neil Armstrong wrote: > > This adds support for the shared USB3 + PCIE PHY found in the > Amlogic G12A SoC Family. > > It supports USB3 Host mode or PCIE 2.0 mode, depending on the layout of > the board. > > Selection is done by the #phy-cells, making the mode static and exclusive. > > Signed-off-by: Neil Armstrong > --- > drivers/phy/amlogic/Kconfig | 12 + > drivers/phy/amlogic/Makefile | 1 + > .../phy/amlogic/phy-meson-g12a-usb3-pcie.c | 414 ++++++++++++++++++ > 3 files changed, 427 insertions(+) > create mode 100644 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c > > diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig > index 78d6e194dce9..7ccb9a756aba 100644 > --- a/drivers/phy/amlogic/Kconfig > +++ b/drivers/phy/amlogic/Kconfig > @@ -48,3 +48,15 @@ config PHY_MESON_G12A_USB2 > Enable this to support the Meson USB2 PHYs found in Meson > G12A SoCs. > If unsure, say N. > + > +config PHY_MESON_G12A_USB3_PCIE > + tristate "Meson G12A USB3+PCIE Combo PHY drivers" nit-pick: s/drivers/driver/ > + default ARCH_MESON > + depends on OF && (ARCH_MESON || COMPILE_TEST) > + depends on USB_SUPPORT > + select GENERIC_PHY > + select REGMAP_MMIO > + help > + Enable this to support the Meson USB3 + PCIE Combi PHY found > + in Meson G12A SoCs. > + If unsure, say N. > diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile > index 7d4d10f5a6b3..fdd008e1b19b 100644 > --- a/drivers/phy/amlogic/Makefile > +++ b/drivers/phy/amlogic/Makefile > @@ -2,3 +2,4 @@ obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o > obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o > obj-$(CONFIG_PHY_MESON_G12A_USB2) += phy-meson-g12a-usb2.o > obj-$(CONFIG_PHY_MESON_GXL_USB3) += phy-meson-gxl-usb3.o > +obj-$(CONFIG_PHY_MESON_G12A_USB3_PCIE) += phy-meson-g12a-usb3-pcie.o > diff --git a/drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c b/drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c > new file mode 100644 > index 000000000000..59eae98928e9 > --- /dev/null > +++ b/drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c > @@ -0,0 +1,414 @@ [...] > +static int phy_g12a_usb3_init(struct phy *phy) > +{ > + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy); > + int data, ret; > + > + /* Switch PHY to USB3 */ > + regmap_update_bits(priv->regmap, PHY_R0, > + PHY_R0_PCIE_USB3_SWITCH, > + PHY_R0_PCIE_USB3_SWITCH); > + > + /* > + * WORKAROUND: There is SSPHY suspend bug due to > + * which USB enumerates > + * in HS mode instead of SS mode. Workaround it by asserting > + * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus > + * mode > + */ > + ret = regmap_update_bits(priv->regmap_cr, 0x102d, BIT(7), BIT(7)); does the datasheet have names for these registers / bits? it if does then it would be great if you could introduce #defines for them > + if (ret) > + return ret; > + > + ret = regmap_update_bits(priv->regmap_cr, 0x1010, 0xff0, 20); > + if (ret) > + return ret; > + > + /* > + * Fix RX Equalization setting as follows > + * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0 > + * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1 > + * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3 > + * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1 > + */ > + ret = regmap_read(priv->regmap_cr, 0x1006, &data); > + if (ret) > + return ret; > + > + data &= ~BIT(6); > + data |= BIT(7); > + data &= ~(0x7 << 8); > + data |= (0x3 << 8); > + data |= (1 << 11); > + ret = regmap_write(priv->regmap_cr, 0x1006, data); > + if (ret) > + return ret; > + > + /* > + * Set EQ and TX launch amplitudes as follows > + * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22 > + * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127 > + * LANE0.TX_OVRD_DRV_LO.EN set to 1. > + */ > + ret = regmap_read(priv->regmap_cr, 0x1002, &data); > + if (ret) > + return ret; > + > + data &= ~0x3f80; > + data |= (0x16 << 7); > + data &= ~0x7f; > + data |= (0x7f | BIT(14)); > + ret = regmap_write(priv->regmap_cr, 0x1002, data); > + if (ret) > + return ret; > + > + /* > + * MPLL_LOOP_CTL.PROP_CNTRL = 8 > + */ why a multi-line comment here? "Switch PHY to USB3" above uses a single-line comment > + ret = regmap_update_bits(priv->regmap_cr, 0x30, 0xf << 4, 8 << 4); > + if (ret) > + return ret; > + > + regmap_update_bits(priv->regmap, PHY_R2, > + PHY_R2_PHY_TX_VBOOST_LVL, > + FIELD_PREP(PHY_R2_PHY_TX_VBOOST_LVL, 0x4)); > + > + regmap_update_bits(priv->regmap, PHY_R1, > + PHY_R1_PHY_LOS_BIAS | PHY_R1_PHY_LOS_LEVEL, > + FIELD_PREP(PHY_R1_PHY_LOS_BIAS, 4) | > + FIELD_PREP(PHY_R1_PHY_LOS_LEVEL, 9)); > + > + return 0; > +} > + > +static int phy_g12a_usb3_pcie_init(struct phy *phy) > +{ > + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy); > + int ret; > + > + ret = reset_control_reset(priv->reset); > + if (ret) > + return ret; > + > + if (priv->mode == PHY_TYPE_USB3) > + return phy_g12a_usb3_init(phy); > + > + /* Power UP PCIE */ > + regmap_update_bits(priv->regmap, PHY_R0, > + PHY_R0_PCIE_POWER_STATE, > + FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c)); do we also need this for USB mode? also do we need to change the PHY_R2 register values (PHY_R2_PHY_TX_VBOOST_LVL for example) for PCIe, for example if the bootloader initialized the PHY in USB3 mode while the board actually exposes a PCIe port? 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Sun, 24 Feb 2019 11:40:48 -0800 (PST) MIME-Version: 1.0 References: <20190212151413.24632-1-narmstrong@baylibre.com> <20190212151413.24632-7-narmstrong@baylibre.com> In-Reply-To: <20190212151413.24632-7-narmstrong@baylibre.com> From: Martin Blumenstingl Date: Sun, 24 Feb 2019 20:40:37 +0100 Message-ID: Subject: Re: [PATCH 6/8] phy: amlogic: Add Amlogic G12A USB3 + PCIE Combo PHY Driver To: Neil Armstrong X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190224_114050_205525_AEA8C490 X-CRM114-Status: GOOD ( 25.81 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: balbi@kernel.org, gregkh@linuxfoundation.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, kishon@ti.com, hminas@synopsys.com, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org Hi Neil, On Tue, Feb 12, 2019 at 4:16 PM Neil Armstrong wrote: > > This adds support for the shared USB3 + PCIE PHY found in the > Amlogic G12A SoC Family. > > It supports USB3 Host mode or PCIE 2.0 mode, depending on the layout of > the board. > > Selection is done by the #phy-cells, making the mode static and exclusive. > > Signed-off-by: Neil Armstrong > --- > drivers/phy/amlogic/Kconfig | 12 + > drivers/phy/amlogic/Makefile | 1 + > .../phy/amlogic/phy-meson-g12a-usb3-pcie.c | 414 ++++++++++++++++++ > 3 files changed, 427 insertions(+) > create mode 100644 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c > > diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig > index 78d6e194dce9..7ccb9a756aba 100644 > --- a/drivers/phy/amlogic/Kconfig > +++ b/drivers/phy/amlogic/Kconfig > @@ -48,3 +48,15 @@ config PHY_MESON_G12A_USB2 > Enable this to support the Meson USB2 PHYs found in Meson > G12A SoCs. > If unsure, say N. > + > +config PHY_MESON_G12A_USB3_PCIE > + tristate "Meson G12A USB3+PCIE Combo PHY drivers" nit-pick: s/drivers/driver/ > + default ARCH_MESON > + depends on OF && (ARCH_MESON || COMPILE_TEST) > + depends on USB_SUPPORT > + select GENERIC_PHY > + select REGMAP_MMIO > + help > + Enable this to support the Meson USB3 + PCIE Combi PHY found > + in Meson G12A SoCs. > + If unsure, say N. > diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile > index 7d4d10f5a6b3..fdd008e1b19b 100644 > --- a/drivers/phy/amlogic/Makefile > +++ b/drivers/phy/amlogic/Makefile > @@ -2,3 +2,4 @@ obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o > obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o > obj-$(CONFIG_PHY_MESON_G12A_USB2) += phy-meson-g12a-usb2.o > obj-$(CONFIG_PHY_MESON_GXL_USB3) += phy-meson-gxl-usb3.o > +obj-$(CONFIG_PHY_MESON_G12A_USB3_PCIE) += phy-meson-g12a-usb3-pcie.o > diff --git a/drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c b/drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c > new file mode 100644 > index 000000000000..59eae98928e9 > --- /dev/null > +++ b/drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c > @@ -0,0 +1,414 @@ [...] > +static int phy_g12a_usb3_init(struct phy *phy) > +{ > + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy); > + int data, ret; > + > + /* Switch PHY to USB3 */ > + regmap_update_bits(priv->regmap, PHY_R0, > + PHY_R0_PCIE_USB3_SWITCH, > + PHY_R0_PCIE_USB3_SWITCH); > + > + /* > + * WORKAROUND: There is SSPHY suspend bug due to > + * which USB enumerates > + * in HS mode instead of SS mode. Workaround it by asserting > + * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus > + * mode > + */ > + ret = regmap_update_bits(priv->regmap_cr, 0x102d, BIT(7), BIT(7)); does the datasheet have names for these registers / bits? it if does then it would be great if you could introduce #defines for them > + if (ret) > + return ret; > + > + ret = regmap_update_bits(priv->regmap_cr, 0x1010, 0xff0, 20); > + if (ret) > + return ret; > + > + /* > + * Fix RX Equalization setting as follows > + * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0 > + * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1 > + * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3 > + * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1 > + */ > + ret = regmap_read(priv->regmap_cr, 0x1006, &data); > + if (ret) > + return ret; > + > + data &= ~BIT(6); > + data |= BIT(7); > + data &= ~(0x7 << 8); > + data |= (0x3 << 8); > + data |= (1 << 11); > + ret = regmap_write(priv->regmap_cr, 0x1006, data); > + if (ret) > + return ret; > + > + /* > + * Set EQ and TX launch amplitudes as follows > + * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22 > + * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127 > + * LANE0.TX_OVRD_DRV_LO.EN set to 1. > + */ > + ret = regmap_read(priv->regmap_cr, 0x1002, &data); > + if (ret) > + return ret; > + > + data &= ~0x3f80; > + data |= (0x16 << 7); > + data &= ~0x7f; > + data |= (0x7f | BIT(14)); > + ret = regmap_write(priv->regmap_cr, 0x1002, data); > + if (ret) > + return ret; > + > + /* > + * MPLL_LOOP_CTL.PROP_CNTRL = 8 > + */ why a multi-line comment here? "Switch PHY to USB3" above uses a single-line comment > + ret = regmap_update_bits(priv->regmap_cr, 0x30, 0xf << 4, 8 << 4); > + if (ret) > + return ret; > + > + regmap_update_bits(priv->regmap, PHY_R2, > + PHY_R2_PHY_TX_VBOOST_LVL, > + FIELD_PREP(PHY_R2_PHY_TX_VBOOST_LVL, 0x4)); > + > + regmap_update_bits(priv->regmap, PHY_R1, > + PHY_R1_PHY_LOS_BIAS | PHY_R1_PHY_LOS_LEVEL, > + FIELD_PREP(PHY_R1_PHY_LOS_BIAS, 4) | > + FIELD_PREP(PHY_R1_PHY_LOS_LEVEL, 9)); > + > + return 0; > +} > + > +static int phy_g12a_usb3_pcie_init(struct phy *phy) > +{ > + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy); > + int ret; > + > + ret = reset_control_reset(priv->reset); > + if (ret) > + return ret; > + > + if (priv->mode == PHY_TYPE_USB3) > + return phy_g12a_usb3_init(phy); > + > + /* Power UP PCIE */ > + regmap_update_bits(priv->regmap, PHY_R0, > + PHY_R0_PCIE_POWER_STATE, > + FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c)); do we also need this for USB mode? also do we need to change the PHY_R2 register values (PHY_R2_PHY_TX_VBOOST_LVL for example) for PCIe, for example if the bootloader initialized the PHY in USB3 mode while the board actually exposes a PCIe port? Regards Martin _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic