From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AF46C43381 for ; Mon, 11 Mar 2019 21:14:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 02D1E2087C for ; Mon, 11 Mar 2019 21:14:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="OiFh82tS" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728071AbfCKVOj (ORCPT ); Mon, 11 Mar 2019 17:14:39 -0400 Received: from mail-oi1-f196.google.com ([209.85.167.196]:41597 "EHLO mail-oi1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727118AbfCKVOj (ORCPT ); Mon, 11 Mar 2019 17:14:39 -0400 Received: by mail-oi1-f196.google.com with SMTP id e7so304026oia.8; Mon, 11 Mar 2019 14:14:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=1LJx1bgWhwnOV4g1ZsjM8oUCFlzqPuh14sDBiNuc0LY=; b=OiFh82tSJQO6TUDjtZPGtofwnpkR+QgQ+ogne/DPoigWMpsw6jLxgm+DO68u/Ag+Mr IYYU49B7qQja0gAsj7LLb3JaQ93yrocjAoGM7dHGhU3y4pPfe4z3lO/1zBdWg+X+bDSU ygbQyMXa1RGAdjww4QjTjY4m64HdWDs9xIyokzqAnea7yZKprOxn4jH33LqB4tOpXrC8 Q0bTDsIL92qXLppjD6l7HQzyrH/t4VRV45i9Hh2vAbyJ/z+J29h5x1eo8pbSrb/rb8LZ 3G53t0LMYavwv16okJc71nw7a8sTBFb3I+ck5vzv7olreYHwJj5h9OsyHApKmnxCf8lR UY/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=1LJx1bgWhwnOV4g1ZsjM8oUCFlzqPuh14sDBiNuc0LY=; b=H5VccBWYyC0d4HDRQmyKQ3IHL8HZu1KwSnxUtJ0KAOEQI0NTZZFUEJ5RUxrsTNqQEA VR3V57ppJ17tfWFQPvutgoJdHpJznqzw0ogzRZTYEQ+AFZHmwLSw3T3KBKhsUeY2NZsk lkkSiGM7mTqo6bXmX3fknHbW6KXYRkm6qOFNZOqlW5if+EPhVo6T1ITRY9gPl2O/+hmS psS/QQ46Wi5LHM+fpCklIoj0Vee4xktHho8HS2pJgftdS2q8czWr6l1lGIl+Uw4T6O3N F1Gx/RlsYzkVRbNmmrAgmn/EthmpdVStBJyH3U78XQoXoNnGNn2qo1EUQ5C3bonUmO4G 4akA== X-Gm-Message-State: APjAAAXC14pcQ/bfQQPNEx0152JjLjH/NV3c2rdafHQ22pvZs/Y3J2Il YCKD/oq+3j+cUpOsNK1Twj54JplH95pLwWyGuUo= X-Google-Smtp-Source: APXvYqwDLrnWKQj+zP1QIGzKJcs55swgmqdCBxD51MwA5D7MjVGxmNy2NoSVkkQzAqGnmi/ijoLBzp5+BJvAX13/LZE= X-Received: by 2002:aca:4205:: with SMTP id p5mr171502oia.15.1552338878194; Mon, 11 Mar 2019 14:14:38 -0700 (PDT) MIME-Version: 1.0 References: <20190304103846.2060-1-narmstrong@baylibre.com> <20190304103846.2060-7-narmstrong@baylibre.com> <6e8b1935-ba91-d06e-be63-cb2632a19654@baylibre.com> In-Reply-To: <6e8b1935-ba91-d06e-be63-cb2632a19654@baylibre.com> From: Martin Blumenstingl Date: Mon, 11 Mar 2019 22:14:27 +0100 Message-ID: Subject: Re: [PATCH v2 6/8] phy: amlogic: Add Amlogic G12A USB3 + PCIE Combo PHY Driver To: Neil Armstrong Cc: gregkh@linuxfoundation.org, hminas@synopsys.com, balbi@kernel.org, kishon@ti.com, linux-amlogic@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Neil, On Thu, Mar 7, 2019 at 9:44 AM Neil Armstrong wrote: > > On 06/03/2019 22:04, Martin Blumenstingl wrote: > > Hi Neil, > > > > On Mon, Mar 4, 2019 at 11:40 AM Neil Armstrong wrote: > > [...] > >> +static int phy_g12a_usb3_init(struct phy *phy) > >> +{ > >> + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy); > >> + int data, ret; > >> + > >> + /* Switch PHY to USB3 */ > >> + regmap_update_bits(priv->regmap, PHY_R0, > >> + PHY_R0_PCIE_USB3_SWITCH, > >> + PHY_R0_PCIE_USB3_SWITCH); > > does this automatically clear PHY_R0_PCIE_POWER_STATE (in case the > > bootloader incorrectly set that)? > > Don't forget it's a static configuration, on the board, only USB3 XOR PCIE > will be available, if the bootloader sets this and the kernel uses USB3, > or the reverse, one of them is wrong. I'm specifically asking is because we've seen various GXL/GXM boards with a bootloader which is configured for the wrong PHY interface (RGMII != RMII) > > > > [...] > >> +static int phy_g12a_usb3_pcie_init(struct phy *phy) > >> +{ > >> + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy); > >> + int ret; > >> + > >> + ret = reset_control_reset(priv->reset); > >> + if (ret) > >> + return ret; > >> + > >> + if (priv->mode == PHY_TYPE_USB3) > >> + return phy_g12a_usb3_init(phy); > >> + > >> + /* Power UP PCIE */ > >> + regmap_update_bits(priv->regmap, PHY_R0, > >> + PHY_R0_PCIE_POWER_STATE, > >> + FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c)); > > similar to my question above: does this automatically clear > > PHY_R0_PCIE_USB3_SWITCH (in case the bootloader incorrectly set that)? > > Same answer, but I'll investigate to have more details on this register. > > It's more an implementation issue, we can change it when PCIe is enabled > on this platform. I'm fine with postponing this until we bring up PCIe support on this platform if you add a comment (preferably marked with "TODO") in the driver. that makes it obvious to everyone who comes across this in the PHY driver with a TODO-comment you can add my: Reviewed-by: Martin Blumenstingl Regards Martin From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v2,6/8] phy: amlogic: Add Amlogic G12A USB3 + PCIE Combo PHY Driver From: Martin Blumenstingl Message-Id: Date: Mon, 11 Mar 2019 22:14:27 +0100 To: Neil Armstrong Cc: gregkh@linuxfoundation.org, hminas@synopsys.com, balbi@kernel.org, kishon@ti.com, linux-amlogic@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-ID: SGkgTmVpbCwKCk9uIFRodSwgTWFyIDcsIDIwMTkgYXQgOTo0NCBBTSBOZWlsIEFybXN0cm9uZyA8 bmFybXN0cm9uZ0BiYXlsaWJyZS5jb20+IHdyb3RlOgo+Cj4gT24gMDYvMDMvMjAxOSAyMjowNCwg TWFydGluIEJsdW1lbnN0aW5nbCB3cm90ZToKPiA+IEhpIE5laWwsCj4gPgo+ID4gT24gTW9uLCBN YXIgNCwgMjAxOSBhdCAxMTo0MCBBTSBOZWlsIEFybXN0cm9uZyA8bmFybXN0cm9uZ0BiYXlsaWJy ZS5jb20+IHdyb3RlOgo+ID4gWy4uLl0KPiA+PiArc3RhdGljIGludCBwaHlfZzEyYV91c2IzX2lu aXQoc3RydWN0IHBoeSAqcGh5KQo+ID4+ICt7Cj4gPj4gKyAgICAgICBzdHJ1Y3QgcGh5X2cxMmFf dXNiM19wY2llX3ByaXYgKnByaXYgPSBwaHlfZ2V0X2RydmRhdGEocGh5KTsKPiA+PiArICAgICAg IGludCBkYXRhLCByZXQ7Cj4gPj4gKwo+ID4+ICsgICAgICAgLyogU3dpdGNoIFBIWSB0byBVU0Iz ICovCj4gPj4gKyAgICAgICByZWdtYXBfdXBkYXRlX2JpdHMocHJpdi0+cmVnbWFwLCBQSFlfUjAs Cj4gPj4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgUEhZX1IwX1BDSUVfVVNCM19TV0lUQ0gs Cj4gPj4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgUEhZX1IwX1BDSUVfVVNCM19TV0lUQ0gp Owo+ID4gZG9lcyB0aGlzIGF1dG9tYXRpY2FsbHkgY2xlYXIgUEhZX1IwX1BDSUVfUE9XRVJfU1RB VEUgKGluIGNhc2UgdGhlCj4gPiBib290bG9hZGVyIGluY29ycmVjdGx5IHNldCB0aGF0KT8KPgo+ IERvbid0IGZvcmdldCBpdCdzIGEgc3RhdGljIGNvbmZpZ3VyYXRpb24sIG9uIHRoZSBib2FyZCwg b25seSBVU0IzIFhPUiBQQ0lFCj4gd2lsbCBiZSBhdmFpbGFibGUsIGlmIHRoZSBib290bG9hZGVy IHNldHMgdGhpcyBhbmQgdGhlIGtlcm5lbCB1c2VzIFVTQjMsCj4gb3IgdGhlIHJldmVyc2UsIG9u ZSBvZiB0aGVtIGlzIHdyb25nLgpJJ20gc3BlY2lmaWNhbGx5IGFza2luZyBpcyBiZWNhdXNlIHdl J3ZlIHNlZW4gdmFyaW91cyBHWEwvR1hNIGJvYXJkcwp3aXRoIGEgYm9vdGxvYWRlciB3aGljaCBp cyBjb25maWd1cmVkIGZvciB0aGUgd3JvbmcgUEhZIGludGVyZmFjZQooUkdNSUkgIT0gUk1JSSkK Cj4gPgo+ID4gWy4uLl0KPiA+PiArc3RhdGljIGludCBwaHlfZzEyYV91c2IzX3BjaWVfaW5pdChz dHJ1Y3QgcGh5ICpwaHkpCj4gPj4gK3sKPiA+PiArICAgICAgIHN0cnVjdCBwaHlfZzEyYV91c2Iz X3BjaWVfcHJpdiAqcHJpdiA9IHBoeV9nZXRfZHJ2ZGF0YShwaHkpOwo+ID4+ICsgICAgICAgaW50 IHJldDsKPiA+PiArCj4gPj4gKyAgICAgICByZXQgPSByZXNldF9jb250cm9sX3Jlc2V0KHByaXYt PnJlc2V0KTsKPiA+PiArICAgICAgIGlmIChyZXQpCj4gPj4gKyAgICAgICAgICAgICAgIHJldHVy biByZXQ7Cj4gPj4gKwo+ID4+ICsgICAgICAgaWYgKHByaXYtPm1vZGUgPT0gUEhZX1RZUEVfVVNC MykKPiA+PiArICAgICAgICAgICAgICAgcmV0dXJuIHBoeV9nMTJhX3VzYjNfaW5pdChwaHkpOwo+ ID4+ICsKPiA+PiArICAgICAgIC8qIFBvd2VyIFVQIFBDSUUgKi8KPiA+PiArICAgICAgIHJlZ21h cF91cGRhdGVfYml0cyhwcml2LT5yZWdtYXAsIFBIWV9SMCwKPiA+PiArICAgICAgICAgICAgICAg ICAgICAgICAgICBQSFlfUjBfUENJRV9QT1dFUl9TVEFURSwKPiA+PiArICAgICAgICAgICAgICAg ICAgICAgICAgICBGSUVMRF9QUkVQKFBIWV9SMF9QQ0lFX1BPV0VSX1NUQVRFLCAweDFjKSk7Cj4g PiBzaW1pbGFyIHRvIG15IHF1ZXN0aW9uIGFib3ZlOiBkb2VzIHRoaXMgYXV0b21hdGljYWxseSBj bGVhcgo+ID4gUEhZX1IwX1BDSUVfVVNCM19TV0lUQ0ggKGluIGNhc2UgdGhlIGJvb3Rsb2FkZXIg aW5jb3JyZWN0bHkgc2V0IHRoYXQpPwo+Cj4gU2FtZSBhbnN3ZXIsIGJ1dCBJJ2xsIGludmVzdGln YXRlIHRvIGhhdmUgbW9yZSBkZXRhaWxzIG9uIHRoaXMgcmVnaXN0ZXIuCj4KPiBJdCdzIG1vcmUg YW4gaW1wbGVtZW50YXRpb24gaXNzdWUsIHdlIGNhbiBjaGFuZ2UgaXQgd2hlbiBQQ0llIGlzIGVu YWJsZWQKPiBvbiB0aGlzIHBsYXRmb3JtLgpJJ20gZmluZSB3aXRoIHBvc3Rwb25pbmcgdGhpcyB1 bnRpbCB3ZSBicmluZyB1cCBQQ0llIHN1cHBvcnQgb24gdGhpcwpwbGF0Zm9ybSBpZiB5b3UgYWRk IGEgY29tbWVudCAocHJlZmVyYWJseSBtYXJrZWQgd2l0aCAiVE9ETyIpIGluIHRoZQpkcml2ZXIu IHRoYXQgbWFrZXMgaXQgb2J2aW91cyB0byBldmVyeW9uZSB3aG8gY29tZXMgYWNyb3NzIHRoaXMg aW4gdGhlClBIWSBkcml2ZXIKCndpdGggYSBUT0RPLWNvbW1lbnQgeW91IGNhbiBhZGQgbXk6ClJl dmlld2VkLWJ5OiBNYXJ0aW4gQmx1bWVuc3RpbmdsIDxtYXJ0aW4uYmx1bWVuc3RpbmdsQGdvb2ds ZW1haWwuY29tPgoKClJlZ2FyZHMKTWFydGluCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A8B8C43381 for ; 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Mon, 11 Mar 2019 14:14:38 -0700 (PDT) MIME-Version: 1.0 References: <20190304103846.2060-1-narmstrong@baylibre.com> <20190304103846.2060-7-narmstrong@baylibre.com> <6e8b1935-ba91-d06e-be63-cb2632a19654@baylibre.com> In-Reply-To: <6e8b1935-ba91-d06e-be63-cb2632a19654@baylibre.com> From: Martin Blumenstingl Date: Mon, 11 Mar 2019 22:14:27 +0100 Message-ID: Subject: Re: [PATCH v2 6/8] phy: amlogic: Add Amlogic G12A USB3 + PCIE Combo PHY Driver To: Neil Armstrong X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190311_141440_448167_35B84848 X-CRM114-Status: GOOD ( 15.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: balbi@kernel.org, gregkh@linuxfoundation.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, kishon@ti.com, hminas@synopsys.com, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Neil, On Thu, Mar 7, 2019 at 9:44 AM Neil Armstrong wrote: > > On 06/03/2019 22:04, Martin Blumenstingl wrote: > > Hi Neil, > > > > On Mon, Mar 4, 2019 at 11:40 AM Neil Armstrong wrote: > > [...] > >> +static int phy_g12a_usb3_init(struct phy *phy) > >> +{ > >> + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy); > >> + int data, ret; > >> + > >> + /* Switch PHY to USB3 */ > >> + regmap_update_bits(priv->regmap, PHY_R0, > >> + PHY_R0_PCIE_USB3_SWITCH, > >> + PHY_R0_PCIE_USB3_SWITCH); > > does this automatically clear PHY_R0_PCIE_POWER_STATE (in case the > > bootloader incorrectly set that)? > > Don't forget it's a static configuration, on the board, only USB3 XOR PCIE > will be available, if the bootloader sets this and the kernel uses USB3, > or the reverse, one of them is wrong. I'm specifically asking is because we've seen various GXL/GXM boards with a bootloader which is configured for the wrong PHY interface (RGMII != RMII) > > > > [...] > >> +static int phy_g12a_usb3_pcie_init(struct phy *phy) > >> +{ > >> + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy); > >> + int ret; > >> + > >> + ret = reset_control_reset(priv->reset); > >> + if (ret) > >> + return ret; > >> + > >> + if (priv->mode == PHY_TYPE_USB3) > >> + return phy_g12a_usb3_init(phy); > >> + > >> + /* Power UP PCIE */ > >> + regmap_update_bits(priv->regmap, PHY_R0, > >> + PHY_R0_PCIE_POWER_STATE, > >> + FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c)); > > similar to my question above: does this automatically clear > > PHY_R0_PCIE_USB3_SWITCH (in case the bootloader incorrectly set that)? > > Same answer, but I'll investigate to have more details on this register. > > It's more an implementation issue, we can change it when PCIe is enabled > on this platform. I'm fine with postponing this until we bring up PCIe support on this platform if you add a comment (preferably marked with "TODO") in the driver. that makes it obvious to everyone who comes across this in the PHY driver with a TODO-comment you can add my: Reviewed-by: Martin Blumenstingl Regards Martin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 134F1C43381 for ; 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Mon, 11 Mar 2019 14:14:38 -0700 (PDT) MIME-Version: 1.0 References: <20190304103846.2060-1-narmstrong@baylibre.com> <20190304103846.2060-7-narmstrong@baylibre.com> <6e8b1935-ba91-d06e-be63-cb2632a19654@baylibre.com> In-Reply-To: <6e8b1935-ba91-d06e-be63-cb2632a19654@baylibre.com> From: Martin Blumenstingl Date: Mon, 11 Mar 2019 22:14:27 +0100 Message-ID: Subject: Re: [PATCH v2 6/8] phy: amlogic: Add Amlogic G12A USB3 + PCIE Combo PHY Driver To: Neil Armstrong X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190311_141440_448167_35B84848 X-CRM114-Status: GOOD ( 15.02 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: balbi@kernel.org, gregkh@linuxfoundation.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, kishon@ti.com, hminas@synopsys.com, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org Hi Neil, On Thu, Mar 7, 2019 at 9:44 AM Neil Armstrong wrote: > > On 06/03/2019 22:04, Martin Blumenstingl wrote: > > Hi Neil, > > > > On Mon, Mar 4, 2019 at 11:40 AM Neil Armstrong wrote: > > [...] > >> +static int phy_g12a_usb3_init(struct phy *phy) > >> +{ > >> + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy); > >> + int data, ret; > >> + > >> + /* Switch PHY to USB3 */ > >> + regmap_update_bits(priv->regmap, PHY_R0, > >> + PHY_R0_PCIE_USB3_SWITCH, > >> + PHY_R0_PCIE_USB3_SWITCH); > > does this automatically clear PHY_R0_PCIE_POWER_STATE (in case the > > bootloader incorrectly set that)? > > Don't forget it's a static configuration, on the board, only USB3 XOR PCIE > will be available, if the bootloader sets this and the kernel uses USB3, > or the reverse, one of them is wrong. I'm specifically asking is because we've seen various GXL/GXM boards with a bootloader which is configured for the wrong PHY interface (RGMII != RMII) > > > > [...] > >> +static int phy_g12a_usb3_pcie_init(struct phy *phy) > >> +{ > >> + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy); > >> + int ret; > >> + > >> + ret = reset_control_reset(priv->reset); > >> + if (ret) > >> + return ret; > >> + > >> + if (priv->mode == PHY_TYPE_USB3) > >> + return phy_g12a_usb3_init(phy); > >> + > >> + /* Power UP PCIE */ > >> + regmap_update_bits(priv->regmap, PHY_R0, > >> + PHY_R0_PCIE_POWER_STATE, > >> + FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c)); > > similar to my question above: does this automatically clear > > PHY_R0_PCIE_USB3_SWITCH (in case the bootloader incorrectly set that)? > > Same answer, but I'll investigate to have more details on this register. > > It's more an implementation issue, we can change it when PCIe is enabled > on this platform. I'm fine with postponing this until we bring up PCIe support on this platform if you add a comment (preferably marked with "TODO") in the driver. that makes it obvious to everyone who comes across this in the PHY driver with a TODO-comment you can add my: Reviewed-by: Martin Blumenstingl Regards Martin _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic