From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57742C636CA for ; Sat, 17 Jul 2021 19:46:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2BB736115C for ; Sat, 17 Jul 2021 19:46:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235198AbhGQTtS (ORCPT ); Sat, 17 Jul 2021 15:49:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34046 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234296AbhGQTtP (ORCPT ); Sat, 17 Jul 2021 15:49:15 -0400 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DEA5C061762; Sat, 17 Jul 2021 12:46:17 -0700 (PDT) Received: by mail-ed1-x536.google.com with SMTP id v1so17477965edt.6; Sat, 17 Jul 2021 12:46:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Uf9ovgwZadCx9qH0j7ni/tLHBwLpSqqtIpLKHpJ2A5k=; b=amz7jyI6NWsc3UfcTGAZpqkYN7ZZ39sstx2gCWuQeDsnK4T5Ds0rAbwzj59MV3qOXS qVBOaKZ2v2IvqGnmHG45Qz/VtbUPE17qbDEoAlnZq3s2G8uVUJfgtKR9iPtmnIe5ysn5 BLzMd6KEt5ugFv4yzpBAFSmWGCLCkxJb/Q/7C65uhvWIGqhce9y0rC+ugflM0C6mC0Xg +fBx+8vWN4IsZzoKP9raOuZ3QwjDUK5navpcxbsZCn3GpNR+6F/5EdOrvXWsr+Wq5R+9 Q//P+eGDC4wTeAwLxtTeytA1HziCt4zF+/uqs4ulnlwH0QRKMQQdvwUymuTTlWDryeiZ oPew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Uf9ovgwZadCx9qH0j7ni/tLHBwLpSqqtIpLKHpJ2A5k=; b=I4rEj4nCss2uMgV9ihp9H7BTRVv5Ba4r1k0ISrLcRfGLysLlQN03Mig4guzBbhFRxQ jD4e8dmAYrbsBz827QZcxr0fscd1Lcy/aT9tPPozsFrzOUWQrKbugIqcK6RhZwkcpjBZ N+wrJwFsWYt8zpX7dYZ+ZnDiDGrMjsB1ABzU4qvl9kTShNl6kvDUmXedj/emBoRe5G4z N/yLsXse/GhoOVIffLuMYjQnOTwsgOBeGfFl1iW1HcieWhto4UcTHOcFPtt+v7s8cfIc xniFaEwBH3d4P80A61paCVcFmXUIiFlBJdjbYXGxFOa7rp0gegw/KTw8Eih8vBbr5zEc ch3Q== X-Gm-Message-State: AOAM530qsbw0c0TtyjCaMUiE3FDJnl6msfD/9RjaXyE6WDS2H64PjW86 alFwU8Yyx4E2vpQ/dXji5nBoylgatWqEYLXrnqw= X-Google-Smtp-Source: ABdhPJwdhDJeG3UUdeAYHhaU+cyLC7AqaAQpYGsHZwnBCdZoSn/tUwKYj1BghaowLSKgddaJsiwEdUkYfnDBaoQm8q8= X-Received: by 2002:aa7:c550:: with SMTP id s16mr23560320edr.130.1626551174723; Sat, 17 Jul 2021 12:46:14 -0700 (PDT) MIME-Version: 1.0 References: <20210716103651.1455-1-linux.amoon@gmail.com> <20210716103651.1455-2-linux.amoon@gmail.com> In-Reply-To: <20210716103651.1455-2-linux.amoon@gmail.com> From: Martin Blumenstingl Date: Sat, 17 Jul 2021 21:46:04 +0200 Message-ID: Subject: Re: [PATCHv2 1/4] ARM: dts: meson8b: odroidc1: Add usb phy power node To: Anand Moon Cc: linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, Matt Corallo , Rob Herring , Neil Armstrong , Kevin Hilman , Jerome Brunet , Kishon Vijay Abraham I , Vinod Koul , Emiliano Ingrassia , Brian Kim , devicetree@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Anand, On Fri, Jul 16, 2021 at 12:37 PM Anand Moon wrote: > > Add missing usb phy power node for phy mode fix below warning. > P5V0 regulator suppy input voltage range to USB host controller. low prio - typo: suppy -> supply > As descriped in the C1+ schematics, GPIO GPIOAO_5 is used to low prio - typo: descriped -> described > enable input power to USB ports, set it to Active Low. > > [ 1.253149] phy phy-c1108820.phy.0: Looking up phy-supply from device tree > [ 1.253166] phy phy-c1108820.phy.0: Looking up phy-supply property > in node /soc/cbus@c1100000/phy@8820 failed high prio: Can you please describe how I can test this patch? My concern is that previously I have tested your patch with ACTIVE_LOW and ACTIVE_HIGH polarity. In both cases USB is working and I cannot observe any change (apart from this debug message being gone). In the Odroid-C1 schematics (page 1) GPIOAO.BIT5 is connected to USB_OTG *only*. I cannot give my Acked-/Reviewed-/Tested-by without a description of how I can actually test the GPIO potion of this patch. [...] > + /* > + * signal name from schematics: PWREN - GPIOAO.BIT5 > + */ > + gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; low prio: Even though it's strictly not necessary I think this is confusing to read. Since there's no "enable-active-high" property the GPIO will be considered as "active low". My suggestion is to change GPIO_ACTIVE_HIGH to GPIO_ACTIVE_LOW Also if you have any extra information since you last pinged me on IRC then it would be great if you could document it. I am referring to these IRC message, where you are stating that the correct polarity should be "active high": xdarklight I have a question on USB GPIO Polarity on Odroid C1+ As per the https://dn.odroid.com/S805/Schematics/odroid-c1+_rev0.4_20160226.pdf MP62551DGT-LF IC controls the power for the USB PORTS https://www.mouser.com/datasheet/2/277/MP62550-1384050.pdf is MP62551DGT datasheet As per the data sheet in section ORDERING INFORMATION Active enable signal is set below MP62551DGT Active High [...] > &usb1_phy { > status = "okay"; > + phy-supply = <&usb_pwr_en>; medium priority: I have raised the following concern in one of my previous emails on this topic: > The mistake I made before is considering USB VBUS as PHY power supply. > I believe the USB PHY is actually powered by the AVDD18_USB_ADC and > USB33_VDDIOH signals. See the S905 datasheet [0], page 25 > These are 1.8V and 3.3V signals while you are adding a 5V regulator. you replied with: > OK, thanks. so I don't understand what "OK, thanks" means. If it means "Martin, you are wrong" then please provide a description so I can also learn something! Best regards, Martin From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.7 required=3.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFF7DC636CA for ; Sat, 17 Jul 2021 19:48:15 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8CEC36044F for ; Sat, 17 Jul 2021 19:48:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8CEC36044F Authentication-Results: mail.kernel.org; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Anand, On Fri, Jul 16, 2021 at 12:37 PM Anand Moon wrote: > > Add missing usb phy power node for phy mode fix below warning. > P5V0 regulator suppy input voltage range to USB host controller. low prio - typo: suppy -> supply > As descriped in the C1+ schematics, GPIO GPIOAO_5 is used to low prio - typo: descriped -> described > enable input power to USB ports, set it to Active Low. > > [ 1.253149] phy phy-c1108820.phy.0: Looking up phy-supply from device tree > [ 1.253166] phy phy-c1108820.phy.0: Looking up phy-supply property > in node /soc/cbus@c1100000/phy@8820 failed high prio: Can you please describe how I can test this patch? My concern is that previously I have tested your patch with ACTIVE_LOW and ACTIVE_HIGH polarity. In both cases USB is working and I cannot observe any change (apart from this debug message being gone). In the Odroid-C1 schematics (page 1) GPIOAO.BIT5 is connected to USB_OTG *only*. I cannot give my Acked-/Reviewed-/Tested-by without a description of how I can actually test the GPIO potion of this patch. [...] > + /* > + * signal name from schematics: PWREN - GPIOAO.BIT5 > + */ > + gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; low prio: Even though it's strictly not necessary I think this is confusing to read. Since there's no "enable-active-high" property the GPIO will be considered as "active low". My suggestion is to change GPIO_ACTIVE_HIGH to GPIO_ACTIVE_LOW Also if you have any extra information since you last pinged me on IRC then it would be great if you could document it. I am referring to these IRC message, where you are stating that the correct polarity should be "active high": xdarklight I have a question on USB GPIO Polarity on Odroid C1+ As per the https://dn.odroid.com/S805/Schematics/odroid-c1+_rev0.4_20160226.pdf MP62551DGT-LF IC controls the power for the USB PORTS https://www.mouser.com/datasheet/2/277/MP62550-1384050.pdf is MP62551DGT datasheet As per the data sheet in section ORDERING INFORMATION Active enable signal is set below MP62551DGT Active High [...] > &usb1_phy { > status = "okay"; > + phy-supply = <&usb_pwr_en>; medium priority: I have raised the following concern in one of my previous emails on this topic: > The mistake I made before is considering USB VBUS as PHY power supply. > I believe the USB PHY is actually powered by the AVDD18_USB_ADC and > USB33_VDDIOH signals. See the S905 datasheet [0], page 25 > These are 1.8V and 3.3V signals while you are adding a 5V regulator. you replied with: > OK, thanks. so I don't understand what "OK, thanks" means. If it means "Martin, you are wrong" then please provide a description so I can also learn something! Best regards, Martin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.7 required=3.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7B10C636CB for ; Sat, 17 Jul 2021 19:46:37 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9675061165 for ; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Uf9ovgwZadCx9qH0j7ni/tLHBwLpSqqtIpLKHpJ2A5k=; b=cpAx8/gMxQmsmrSgvkTQ2uz4v8hOfwLYZNvw2PSrzjcONFi2o/FIDDpbLNw5WZaqeb AjAU0s4SBEKi5vOKK1xPlqglY5ZQNqed3WD2sDtM6BRr29R605ofIIzIXJriIpxQvYKr SC0dN6I5uBaQrD/tn7Z+IYna3jWugNgLRcQZgMbG9gW5YAiVBbOU0VwmfM1qoyRxF76t xbCqQOyOQl0qyDM0Wy6GGKTiuUbzMZGZ9H3p5SDIyBBSJddnnI3JYQ0U/2mwwPEs1Qup G/dMGrwqYwHaCZsUETRoG2DEMAQMqI4x8EJqZpNMxtf56F0AH6sYHza36f0PiMWodGnD WwWw== X-Gm-Message-State: AOAM532ZgAGbGCJ0i3uAUiUtTpp/eZZzTAv+QKedpbCJ/0Oz1IN8T2kf GN4qinXbCXduUsSlpOzor2oeN1LGT7PBharCKxQ= X-Google-Smtp-Source: ABdhPJwdhDJeG3UUdeAYHhaU+cyLC7AqaAQpYGsHZwnBCdZoSn/tUwKYj1BghaowLSKgddaJsiwEdUkYfnDBaoQm8q8= X-Received: by 2002:aa7:c550:: with SMTP id s16mr23560320edr.130.1626551174723; Sat, 17 Jul 2021 12:46:14 -0700 (PDT) MIME-Version: 1.0 References: <20210716103651.1455-1-linux.amoon@gmail.com> <20210716103651.1455-2-linux.amoon@gmail.com> In-Reply-To: <20210716103651.1455-2-linux.amoon@gmail.com> From: Martin Blumenstingl Date: Sat, 17 Jul 2021 21:46:04 +0200 Message-ID: Subject: Re: [PATCHv2 1/4] ARM: dts: meson8b: odroidc1: Add usb phy power node To: Anand Moon Cc: linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, Matt Corallo , Rob Herring , Neil Armstrong , Kevin Hilman , Jerome Brunet , Kishon Vijay Abraham I , Vinod Koul , Emiliano Ingrassia , Brian Kim , devicetree@vger.kernel.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210717_124617_549513_3CAB3010 X-CRM114-Status: GOOD ( 20.28 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org Hi Anand, On Fri, Jul 16, 2021 at 12:37 PM Anand Moon wrote: > > Add missing usb phy power node for phy mode fix below warning. > P5V0 regulator suppy input voltage range to USB host controller. low prio - typo: suppy -> supply > As descriped in the C1+ schematics, GPIO GPIOAO_5 is used to low prio - typo: descriped -> described > enable input power to USB ports, set it to Active Low. > > [ 1.253149] phy phy-c1108820.phy.0: Looking up phy-supply from device tree > [ 1.253166] phy phy-c1108820.phy.0: Looking up phy-supply property > in node /soc/cbus@c1100000/phy@8820 failed high prio: Can you please describe how I can test this patch? My concern is that previously I have tested your patch with ACTIVE_LOW and ACTIVE_HIGH polarity. In both cases USB is working and I cannot observe any change (apart from this debug message being gone). In the Odroid-C1 schematics (page 1) GPIOAO.BIT5 is connected to USB_OTG *only*. I cannot give my Acked-/Reviewed-/Tested-by without a description of how I can actually test the GPIO potion of this patch. [...] > + /* > + * signal name from schematics: PWREN - GPIOAO.BIT5 > + */ > + gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; low prio: Even though it's strictly not necessary I think this is confusing to read. Since there's no "enable-active-high" property the GPIO will be considered as "active low". My suggestion is to change GPIO_ACTIVE_HIGH to GPIO_ACTIVE_LOW Also if you have any extra information since you last pinged me on IRC then it would be great if you could document it. I am referring to these IRC message, where you are stating that the correct polarity should be "active high": xdarklight I have a question on USB GPIO Polarity on Odroid C1+ As per the https://dn.odroid.com/S805/Schematics/odroid-c1+_rev0.4_20160226.pdf MP62551DGT-LF IC controls the power for the USB PORTS https://www.mouser.com/datasheet/2/277/MP62550-1384050.pdf is MP62551DGT datasheet As per the data sheet in section ORDERING INFORMATION Active enable signal is set below MP62551DGT Active High [...] > &usb1_phy { > status = "okay"; > + phy-supply = <&usb_pwr_en>; medium priority: I have raised the following concern in one of my previous emails on this topic: > The mistake I made before is considering USB VBUS as PHY power supply. > I believe the USB PHY is actually powered by the AVDD18_USB_ADC and > USB33_VDDIOH signals. See the S905 datasheet [0], page 25 > These are 1.8V and 3.3V signals while you are adding a 5V regulator. you replied with: > OK, thanks. so I don't understand what "OK, thanks" means. If it means "Martin, you are wrong" then please provide a description so I can also learn something! Best regards, Martin _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.7 required=3.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B459DC636C9 for ; Sat, 17 Jul 2021 19:46:20 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 64E8A6044F for ; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Uf9ovgwZadCx9qH0j7ni/tLHBwLpSqqtIpLKHpJ2A5k=; b=cpAx8/gMxQmsmrSgvkTQ2uz4v8hOfwLYZNvw2PSrzjcONFi2o/FIDDpbLNw5WZaqeb AjAU0s4SBEKi5vOKK1xPlqglY5ZQNqed3WD2sDtM6BRr29R605ofIIzIXJriIpxQvYKr SC0dN6I5uBaQrD/tn7Z+IYna3jWugNgLRcQZgMbG9gW5YAiVBbOU0VwmfM1qoyRxF76t xbCqQOyOQl0qyDM0Wy6GGKTiuUbzMZGZ9H3p5SDIyBBSJddnnI3JYQ0U/2mwwPEs1Qup G/dMGrwqYwHaCZsUETRoG2DEMAQMqI4x8EJqZpNMxtf56F0AH6sYHza36f0PiMWodGnD WwWw== X-Gm-Message-State: AOAM532ZgAGbGCJ0i3uAUiUtTpp/eZZzTAv+QKedpbCJ/0Oz1IN8T2kf GN4qinXbCXduUsSlpOzor2oeN1LGT7PBharCKxQ= X-Google-Smtp-Source: ABdhPJwdhDJeG3UUdeAYHhaU+cyLC7AqaAQpYGsHZwnBCdZoSn/tUwKYj1BghaowLSKgddaJsiwEdUkYfnDBaoQm8q8= X-Received: by 2002:aa7:c550:: with SMTP id s16mr23560320edr.130.1626551174723; Sat, 17 Jul 2021 12:46:14 -0700 (PDT) MIME-Version: 1.0 References: <20210716103651.1455-1-linux.amoon@gmail.com> <20210716103651.1455-2-linux.amoon@gmail.com> In-Reply-To: <20210716103651.1455-2-linux.amoon@gmail.com> From: Martin Blumenstingl Date: Sat, 17 Jul 2021 21:46:04 +0200 Message-ID: Subject: Re: [PATCHv2 1/4] ARM: dts: meson8b: odroidc1: Add usb phy power node To: Anand Moon Cc: linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, Matt Corallo , Rob Herring , Neil Armstrong , Kevin Hilman , Jerome Brunet , Kishon Vijay Abraham I , Vinod Koul , Emiliano Ingrassia , Brian Kim , devicetree@vger.kernel.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210717_124617_549513_3CAB3010 X-CRM114-Status: GOOD ( 20.28 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Hi Anand, On Fri, Jul 16, 2021 at 12:37 PM Anand Moon wrote: > > Add missing usb phy power node for phy mode fix below warning. > P5V0 regulator suppy input voltage range to USB host controller. low prio - typo: suppy -> supply > As descriped in the C1+ schematics, GPIO GPIOAO_5 is used to low prio - typo: descriped -> described > enable input power to USB ports, set it to Active Low. > > [ 1.253149] phy phy-c1108820.phy.0: Looking up phy-supply from device tree > [ 1.253166] phy phy-c1108820.phy.0: Looking up phy-supply property > in node /soc/cbus@c1100000/phy@8820 failed high prio: Can you please describe how I can test this patch? My concern is that previously I have tested your patch with ACTIVE_LOW and ACTIVE_HIGH polarity. In both cases USB is working and I cannot observe any change (apart from this debug message being gone). In the Odroid-C1 schematics (page 1) GPIOAO.BIT5 is connected to USB_OTG *only*. I cannot give my Acked-/Reviewed-/Tested-by without a description of how I can actually test the GPIO potion of this patch. [...] > + /* > + * signal name from schematics: PWREN - GPIOAO.BIT5 > + */ > + gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; low prio: Even though it's strictly not necessary I think this is confusing to read. Since there's no "enable-active-high" property the GPIO will be considered as "active low". My suggestion is to change GPIO_ACTIVE_HIGH to GPIO_ACTIVE_LOW Also if you have any extra information since you last pinged me on IRC then it would be great if you could document it. I am referring to these IRC message, where you are stating that the correct polarity should be "active high": xdarklight I have a question on USB GPIO Polarity on Odroid C1+ As per the https://dn.odroid.com/S805/Schematics/odroid-c1+_rev0.4_20160226.pdf MP62551DGT-LF IC controls the power for the USB PORTS https://www.mouser.com/datasheet/2/277/MP62550-1384050.pdf is MP62551DGT datasheet As per the data sheet in section ORDERING INFORMATION Active enable signal is set below MP62551DGT Active High [...] > &usb1_phy { > status = "okay"; > + phy-supply = <&usb_pwr_en>; medium priority: I have raised the following concern in one of my previous emails on this topic: > The mistake I made before is considering USB VBUS as PHY power supply. > I believe the USB PHY is actually powered by the AVDD18_USB_ADC and > USB33_VDDIOH signals. See the S905 datasheet [0], page 25 > These are 1.8V and 3.3V signals while you are adding a 5V regulator. you replied with: > OK, thanks. so I don't understand what "OK, thanks" means. If it means "Martin, you are wrong" then please provide a description so I can also learn something! Best regards, Martin -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy