From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32993) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VS9YV-0001hU-Mb for qemu-devel@nongnu.org; Fri, 04 Oct 2013 13:52:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VS9YR-0002tX-GP for qemu-devel@nongnu.org; Fri, 04 Oct 2013 13:52:47 -0400 Received: from mail-la0-f45.google.com ([209.85.215.45]:35654) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VS9YR-0002tR-8n for qemu-devel@nongnu.org; Fri, 04 Oct 2013 13:52:43 -0400 Received: by mail-la0-f45.google.com with SMTP id eh20so3509290lab.4 for ; Fri, 04 Oct 2013 10:52:42 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1380905823-3981-5-git-send-email-chouteau@adacore.com> References: <1380905823-3981-1-git-send-email-chouteau@adacore.com> <1380905823-3981-5-git-send-email-chouteau@adacore.com> From: Peter Maydell Date: Sat, 5 Oct 2013 02:52:22 +0900 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH 4/4] Add ARM registers definitions for Monitor commands List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Fabien Chouteau Cc: QEMU Developers , =?UTF-8?Q?Andreas_F=C3=A4rber?= , Luiz Capitulino On 5 October 2013 01:57, Fabien Chouteau wrote: > > Signed-off-by: Fabien Chouteau > --- > target-arm/Makefile.objs | 2 +- > target-arm/cpu.c | 7 +++++++ > target-arm/monitor.c | 40 ++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 48 insertions(+), 1 deletion(-) > create mode 100644 target-arm/monitor.c > > diff --git a/target-arm/Makefile.objs b/target-arm/Makefile.objs > index 6453f5c..6c3ec32 100644 > --- a/target-arm/Makefile.objs > +++ b/target-arm/Makefile.objs > @@ -1,5 +1,5 @@ > obj-y += arm-semi.o > -obj-$(CONFIG_SOFTMMU) += machine.o > +obj-$(CONFIG_SOFTMMU) += machine.o monitor.o > obj-$(CONFIG_KVM) += kvm.o > obj-$(CONFIG_NO_KVM) += kvm-stub.o > obj-y += translate.o op_helper.o helper.o cpu.o > diff --git a/target-arm/cpu.c b/target-arm/cpu.c > index d40f2a7..bb15ee8 100644 > --- a/target-arm/cpu.c > +++ b/target-arm/cpu.c > @@ -26,6 +26,9 @@ > #include "hw/arm/arm.h" > #include "sysemu/sysemu.h" > #include "sysemu/kvm.h" > +#include "monitor/monitor_def.h" > + > +extern const MonitorDef arm_monitor_defs[]; > > static void arm_cpu_set_pc(CPUState *cs, vaddr value) > { > @@ -217,6 +220,10 @@ static void arm_cpu_initfn(Object *obj) > ARRAY_SIZE(cpu->gt_timer_outputs)); > #endif > > +#if !defined(CONFIG_USER_ONLY) > + cs->monitor_defs = arm_monitor_defs; > +#endif > + > if (tcg_enabled() && !inited) { > inited = true; > arm_translate_init(); > diff --git a/target-arm/monitor.c b/target-arm/monitor.c > new file mode 100644 > index 0000000..0d68a14 > --- /dev/null > +++ b/target-arm/monitor.c > @@ -0,0 +1,40 @@ > +/* > + * ARM MonitorDef > + * > + * Copyright (c) 2013 AdaCore > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see . > + */ > + > +#include "monitor/monitor_def.h" > + > +const MonitorDef arm_monitor_defs[] = { > + { "r0", offsetof(CPUARMState, regs[0]) }, > + { "r1", offsetof(CPUARMState, regs[1]) }, These fields are all 32 bits, not target_long, so they need to be marked as MD_I32. (If you build an aarch64-softmmu target then it will have target_long be 64 bit but still support all the 32 bit CPUs, so it does make a difference.) thanks -- PMM