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From: Peter Maydell <peter.maydell@linaro.org>
Date: Wed, 13 Dec 2017 10:27:30 +0000
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Subject: Re: [Qemu-devel] [PATCH-2.12 v3 0/3] Update the reset values of the
 Xilinx ZynqMP QSPI
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To: Alistair Francis <alistair.francis@xilinx.com>
Cc: QEMU Developers <qemu-devel@nongnu.org>, Edgar Iglesias <edgar.iglesias@xilinx.com>, "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, Alistair Francis <alistair23@gmail.com>, KONRAD Frederic <frederic.konrad@adacore.com>, Francisco Iglesias <frasse.iglesias@gmail.com>

On 12 December 2017 at 18:54, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> Update the reset values of the Xilinx ZynqMP QSPI device to match the
> resister spec here:
> https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html
>
> V3:
>  - Match documented name
> V2:
>  - Don't double set registers
>
> Based-on: 20171126231634.9531-14-frasse.iglesias@gmail.com



Applied to target-arm.next, thanks.

-- PMM