From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34109) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bFRc6-00048x-5e for qemu-devel@nongnu.org; Tue, 21 Jun 2016 15:45:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bFRc4-0002di-8B for qemu-devel@nongnu.org; Tue, 21 Jun 2016 15:45:33 -0400 Received: from mail-vk0-x232.google.com ([2607:f8b0:400c:c05::232]:35014) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bFRc3-0002dL-It for qemu-devel@nongnu.org; Tue, 21 Jun 2016 15:45:32 -0400 Received: by mail-vk0-x232.google.com with SMTP id j2so34495115vkg.2 for ; Tue, 21 Jun 2016 12:45:31 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: From: Peter Maydell Date: Tue, 21 Jun 2016 20:45:09 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH v6 06/13] register: Add block initialise helper List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alistair Francis Cc: Edgar Iglesias , QEMU Developers , Peter Crosthwaite , "Edgar E. Iglesias" , =?UTF-8?B?QWxleCBCZW5uw6ll?= , =?UTF-8?Q?Andreas_F=C3=A4rber?= , =?UTF-8?B?S09OUkFEIEZyw6lkw6lyaWM=?= On 21 June 2016 at 19:25, Alistair Francis wrote: > On Fri, Jun 10, 2016 at 4:02 AM, Peter Maydell wrote: >>> +/** >>> + * Init a block of consecutive registers into a container MemoryRegion. A >>> + * number of constant register definitions are parsed to create a corresponding >>> + * array of RegisterInfo's. >>> + * >>> + * @owner: device owning the registers >>> + * @rae: Register definitions to init >>> + * @num: number of registers to init (length of @rae) >>> + * @ri: Register array to init >>> + * @data: Array to use for register data >>> + * @container: Memory region to contain new registers >>> + * @ops: Memory region ops to access registers. >>> + * @debug enabled: turn on/off verbose debug information >>> + */ >>> + >>> +void register_init_block32(DeviceState *owner, const RegisterAccessInfo *rae, >>> + int num, RegisterInfo *ri, uint32_t *data, >>> + MemoryRegion *container, const MemoryRegionOps *ops, >>> + bool debug_enabled, uint64_t memory_size); >> >> This doesn't seem to contemplate register arrays which are mostly >> consecutive but have some unimplemented/reserved regions. > > I disagree, we only init registers that are described in the device. > Doing work for blank spaces seems unnecessary. It says "consecutive registers" -- if that doesn't mean "all these registers have to be in a single block what does it mean? thanks -- PMM