From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58453) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YfPfg-0005mq-4b for qemu-devel@nongnu.org; Tue, 07 Apr 2015 05:19:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YfPfb-00014x-Tw for qemu-devel@nongnu.org; Tue, 07 Apr 2015 05:19:48 -0400 Received: from mail-ie0-f169.google.com ([209.85.223.169]:35029) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YfPfb-00014p-PL for qemu-devel@nongnu.org; Tue, 07 Apr 2015 05:19:43 -0400 Received: by ierf6 with SMTP id f6so41274037ier.2 for ; Tue, 07 Apr 2015 02:19:43 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <55234469.9060404@huawei.com> References: <1428055432-12120-1-git-send-email-zhaoshenglong@huawei.com> <1428346052.2973.26.camel@deneb.redhat.com> <55234469.9060404@huawei.com> From: Peter Maydell Date: Tue, 7 Apr 2015 10:19:22 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Shannon Zhao Cc: hangaohuai@huawei.com, Igor Mammedov , Alexander Spyridakis , "Michael S. Tsirkin" , Claudio Fontana , QEMU Developers , "Huangpeng (Peter)" , Hanjun Guo , Mark Salter , Paolo Bonzini , Laszlo Ersek , Christoffer Dall , Shannon Zhao On 7 April 2015 at 03:43, Shannon Zhao wrote: > The dts node is: > ranges = <0x1000000 0x0 0x0 0x0 0x3eff0000 0x0 0x10000 > 0x2000000 0x0 0x10000000 0x0 0x10000000 0x0 0x2eff0000>; > reg = <0x0 0x3f000000 0x0 0x1000000>; > bus-range = <0x0 0xf>; > > The ACPI table entry: > Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address > { > Return (0x3F000000) > } > Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings > { > Name (RBUF, ResourceTemplate () > { > WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, > 0x0000, // Granularity > 0x0000, // Range Minimum > 0x000F, // Range Maximum > 0x0000, // Translation Offset > 0x0010, // Length > ,, ) > DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, Is this claiming that the non-cacheable PCI MMIO region is cacheable? If so that isn't right... > 0x00000000, // Granularity > 0x10000000, // Range Minimum > 0x3EFF0000, // Range Maximum > 0x00000000, // Translation Offset > 0x2EFF0000, // Length > ,, , AddressRangeMemory, TypeStatic) > DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, > 0x00000000, // Granularity > 0x3EFF0000, // Range Minimum > 0x3F000000, // Range Maximum > 0x00000000, // Translation Offset I rather suspect this is wrong, since (my guess without looking at the spec) it looks like it defines a 1:1 mapping between the addresses used to interact with the PCIe IO window and the IO addresses, which is obviously not what you want. My guess is you need to set the translation offset at least, but check the spec. -- PMM