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Date: Thu, 15 Mar 2012 19:20:46 +0000
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From: Peter Maydell <peter.maydell@linaro.org>
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Subject: Re: [Qemu-devel] [PATCH RFC v4 08/20] target-arm: Store cp15 c0_c1
	and c0_c2 in ARMCPUClass
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To: Paul Brook <paul@codesourcery.com>
Cc: =?UTF-8?Q?Andreas_F=C3=A4rber?= <afaerber@suse.de>, qemu-devel@nongnu.org

On 15 March 2012 19:08, Paul Brook <paul@codesourcery.com> wrote:
>> For now set them in the reset function.
>
>> + =C2=A0 =C2=A0/* TODO Move these into arm_cpu_initfn() once no longer z=
eroed above.*/
>> + =C2=A0 =C2=A0memcpy(env->cp15.c0_c1, klass->cp15.c0_c1, 8 * sizeof(uin=
t32_t));
>> + =C2=A0 =C2=A0memcpy(env->cp15.c0_c2, klass->cp15.c0_c2, 8 * sizeof(uin=
t32_t)); +
>
> Why bother copying them into the CPU state? =C2=A0These are readonly, so =
anything
> that needs them should be able to use the value straight from the class
> definitions.

In my (hugely delayed) cp15 rework attempt these probably go away anyway
in favour of having each CPU register a pile of registers along the lines o=
f

    { .name =3D "ID_PFR0", .cp =3D 15, .crn =3D 0, .crm =3D 1, .opc1 =3D 0,=
 .opc2 =3D 0,
      .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0x00001231=
 },
    { .name =3D "ID_PFR1", .cp =3D 15, .crn =3D 0, .crm =3D 1, .opc1 =3D 0,=
 .opc2 =3D 1,
      .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0x00000011=
 },
etc.

I'm not sure there's any need to retain the CPUState (or equivalent) fields
for them at that point.

-- PMM