From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39087) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WfrMw-0004M6-7B for qemu-devel@nongnu.org; Thu, 01 May 2014 09:49:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WfrMr-0005TZ-C5 for qemu-devel@nongnu.org; Thu, 01 May 2014 09:49:46 -0400 Received: from mail-la0-f42.google.com ([209.85.215.42]:54621) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WfrMr-0005TM-5A for qemu-devel@nongnu.org; Thu, 01 May 2014 09:49:41 -0400 Received: by mail-la0-f42.google.com with SMTP id mc6so2219117lab.1 for ; Thu, 01 May 2014 06:49:39 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1398362083-17737-1-git-send-email-peter.maydell@linaro.org> References: <1398362083-17737-1-git-send-email-peter.maydell@linaro.org> From: Peter Maydell Date: Thu, 1 May 2014 14:49:19 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH 0/3] hw/arm/virt: Support Cortex-A57 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: QEMU Developers Cc: Rob Herring , Peter Crosthwaite , "kvmarm@lists.cs.columbia.edu" , Patch Tracking On 24 April 2014 18:54, Peter Maydell wrote: > This patchset wires up our new Cortex-A57 emulation into > the "virt" machine model. Rather than the somewhat hacky > approach in the previous system emulation patchsets, I've > decided that our best approach is to have the board model > create the GIC itself. This essentially corresponds to > modelling a board with a standalone GIC -- you can see > this in some real hardware which uses a GIC-400. I think > this makes more sense than either borrowing the a15mpcore_priv > device, or creating an a57mpcore_priv device (since the A57 > does not actually have a built-in GICv2). > > To handle hosts with 64K pages in KVM mode, we need to > amke sure our GIC puts its GICC and GICD at 64K boundaries > (so that the host kernel can map a 64K host page with the > host GICV in as the guest GICC). > > For consistency, we make the 'virt' machine's GIC the > same for all supported CPUs; 32 bit CPUs don't need > the 64K spacing, but they don't object to it either, and > it's simpler to use the same memory map for everything > rather than fiddle with it based on CPU features. > > Peter Maydell (3): > hw/arm/virt: Create the GIC ourselves rather than (ab)using > a15mpcore_priv > hw/arm/virt: Put GIC register banks on 64K boundaries > hw/arm/virt: Add support for Cortex-A57 > > hw/arm/virt.c | 93 +++++++++++++++++++++++++++++++++++++++-------------------- > 1 file changed, 61 insertions(+), 32 deletions(-) Applying to target-arm.next... thanks -- PMM