From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56995) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aYwzb-0004o8-BA for qemu-devel@nongnu.org; Thu, 25 Feb 2016 09:34:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aYwza-0000QK-J5 for qemu-devel@nongnu.org; Thu, 25 Feb 2016 09:34:11 -0500 Received: from mail-vk0-x236.google.com ([2607:f8b0:400c:c05::236]:34447) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aYwza-0000QC-AH for qemu-devel@nongnu.org; Thu, 25 Feb 2016 09:34:10 -0500 Received: by mail-vk0-x236.google.com with SMTP id e185so48862704vkb.1 for ; Thu, 25 Feb 2016 06:34:10 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <7e53a8579626017e62bfa696ca343c310360afa8.1455534309.git.jcd@tribudubois.net> References: <7e53a8579626017e62bfa696ca343c310360afa8.1455534309.git.jcd@tribudubois.net> From: Peter Maydell Date: Thu, 25 Feb 2016 14:33:49 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH v2 4/4] i.MX: Add SPI NOR FLASH memory to sabrelite board. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jean-Christophe Dubois Cc: QEMU Developers , Peter Crosthwaite On 15 February 2016 at 11:18, Jean-Christophe Dubois wrote: > Signed-off-by: Jean-Christophe Dubois > --- > > Changes since v1: > * Not present on v1. > > hw/arm/sabrelite.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c > index 8db9bbc..237dfa1 100644 > --- a/hw/arm/sabrelite.c > +++ b/hw/arm/sabrelite.c > @@ -70,6 +70,15 @@ static void sabrelite_init(MachineState *machine) > memory_region_add_subregion(get_system_memory(), FSL_IMX6_MMDC_ADDR, > &s->ram); > > + { > + /* Add the sst25vf016b NOR FLASH memory to first SPI */ > + SSIBus *spi = (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc.spi[0]), > + "spi"); Rather than having the board code looking into the internals of the SoC struct like this, you should have the SoC create an spi bus property for itself, and then here you can just have spibus = (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), "spi"); See hw/arm/xlnx-ep108.c for an example of this. The code to create the property in the SoC's realize method is object_property_add_alias(OBJECT(s), "spi", OBJECT(&s->spi[i]), "spi", &error_abort); (where the first "spi" is the name of the bus property to create on the SoC object, and the second is the name of the bus property on the internal SPI device object). Example code in hw/arm/xlnx-zynqmp.c. > + DeviceState *flash_dev = ssi_create_slave(spi, "sst25vf016b"); > + qemu_irq cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi[0]), 1, cs_line); Again, you want the SoC to provide an outward-facing interface to the chipselect line so you don't have to have the board code looking into soc.spi[] itself. > + } > + > sabrelite_binfo.ram_size = machine->ram_size; > sabrelite_binfo.kernel_filename = machine->kernel_filename; > sabrelite_binfo.kernel_cmdline = machine->kernel_cmdline; thanks -- PMM