From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42179) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YuOuB-0001Gj-5x for qemu-devel@nongnu.org; Mon, 18 May 2015 13:32:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YuOu6-0003Op-Sw for qemu-devel@nongnu.org; Mon, 18 May 2015 13:32:43 -0400 Received: from mail-ig0-f172.google.com ([209.85.213.172]:38898) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YuOu6-0003Oe-O4 for qemu-devel@nongnu.org; Mon, 18 May 2015 13:32:38 -0400 Received: by igcau1 with SMTP id au1so53690524igc.1 for ; Mon, 18 May 2015 10:32:38 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1429722561-12651-5-git-send-email-greg.bellows@linaro.org> References: <1429722561-12651-1-git-send-email-greg.bellows@linaro.org> <1429722561-12651-5-git-send-email-greg.bellows@linaro.org> From: Peter Maydell Date: Mon, 18 May 2015 18:32:17 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH v2 4/9] target-arm: Add AArch64 CPTR registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Greg Bellows Cc: Sergey Fedorov , =?UTF-8?B?QWxleCBCZW5uw6ll?= , QEMU Developers On 22 April 2015 at 18:09, Greg Bellows wrote: > Adds CPTR_EL2/3 system registers definitions and access function. > > Signed-off-by: Greg Bellows > > --- > > v2 -> v3 > - Broke out cptr and cpacr access functions > - Added HCPTR register entry as alias of CPTR_EL2 > - Added HCPTR and CPTR_EL2 no_el2 register entries. > - Fixed cptr_access comment > --- > target-arm/cpu.h | 5 +++++ > target-arm/helper.c | 50 +++++++++++++++++++++++++++++++++++++++++++++++++- > 2 files changed, 54 insertions(+), 1 deletion(-) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 2178a1f..d61bb3f 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -202,6 +202,7 @@ typedef struct CPUARMState { > uint64_t sctlr_el[4]; > }; > uint64_t c1_coproc; /* Coprocessor access register. */ > + uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ > uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ > uint64_t sder; /* Secure debug enable register. */ > uint32_t nsacr; /* Non-secure access control register. */ > @@ -575,6 +576,10 @@ void pmccntr_sync(CPUARMState *env); > #define SCTLR_AFE (1U << 29) > #define SCTLR_TE (1U << 30) > > +#define CPTR_TCPAC (1U << 31) > +#define CPTR_TTA (1U << 20) > +#define CPTR_TFP (1U << 10) > + > #define CPSR_M (0x1fU) > #define CPSR_T (1U << 5) > #define CPSR_F (1U << 6) > diff --git a/target-arm/helper.c b/target-arm/helper.c > index c83d9fc..e36c3d4 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -592,6 +592,34 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, > env->cp15.c1_coproc = value; > } > > +static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri) > +{ > + if (arm_feature(env, ARM_FEATURE_V8) && arm_current_el(env) == 1) { > + /* Check if CPACR accesses are to be trapped to EL2 */ > + if ((env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) { > + env->exception.target_el = 2; > + return CP_ACCESS_TRAP; > + /* Check if CPACR accesses are to be trapped to EL3 */ > + } else if (env->cp15.cptr_el[3] & CPTR_TCPAC) { CPTR_EL3.TCPAC traps EL2 accesses to CPACR as well as EL1 accesses. > + env->exception.target_el = 3; > + return CP_ACCESS_TRAP; > + } > + } > + > + return CP_ACCESS_OK; > +} > + > +static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri) > +{ > + /* Check it CPTR accesses are set to trap to EL3 */ "if" > + if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) { > + env->exception.target_el = 3; > + return CP_ACCESS_TRAP; > + } > + > + return CP_ACCESS_OK; > +} > + > static const ARMCPRegInfo v6_cp_reginfo[] = { > /* prefetch by MVA in v6, NOP in v7 */ > { .name = "MVA_prefetch", > @@ -614,7 +642,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] = { > { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, > .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, > { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, > - .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, > + .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, > .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc), > .resetvalue = 0, .writefn = cpacr_write }, > REGINFO_SENTINEL > @@ -2470,6 +2498,14 @@ static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = { > .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, > .access = PL2_RW, > .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, > + { .name = "CPTR_EL2", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, > + .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, > + .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, > + { .name = "HCPTR", .type = ARM_CP_ALIAS, > + .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, > + .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, > + .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, These can be merged into a single ARM_CP_STATE_BOTH, using ARM_CP_CONST is more efficient than using readfns to get the RAZ/WI behaviour, and we don't need the access function because it can never trigger for a CPU without EL2: + { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, + .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, > REGINFO_SENTINEL > }; > > @@ -2537,6 +2573,14 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { > .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, > .access = PL3_RW, .type = ARM_CP_ALIAS, > .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, > + { .name = "CPTR_EL2", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, > + .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, > + .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) }, > + { .name = "HCPTR", .type = ARM_CP_ALIAS, > + .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, > + .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, > + .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) }, These also can be merged: + { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, + .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) }, > REGINFO_SENTINEL > }; > > @@ -2598,6 +2642,10 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { > .access = PL3_RW, .writefn = vbar_write, > .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), > .resetvalue = 0 }, > + { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2, > + .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0, > + .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) }, > REGINFO_SENTINEL > }; thanks -- PMM