From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F6EBC433ED for ; Tue, 11 May 2021 12:43:18 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8FC3A6121E for ; Tue, 11 May 2021 12:43:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8FC3A6121E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:60940 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lgRjI-0001fC-GP for qemu-devel@archiver.kernel.org; Tue, 11 May 2021 08:43:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44912) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lgRi4-0008Qj-SZ for qemu-devel@nongnu.org; Tue, 11 May 2021 08:42:00 -0400 Received: from mail-ed1-x536.google.com ([2a00:1450:4864:20::536]:43983) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lgRi2-0005GV-3H for qemu-devel@nongnu.org; Tue, 11 May 2021 08:42:00 -0400 Received: by mail-ed1-x536.google.com with SMTP id s6so22648022edu.10 for ; Tue, 11 May 2021 05:41:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=jkVMGHM2OFM3PfvMFosGHx1y7xB7uCorpA1+ExyeYa0=; b=NGyFPW6OQbxzVTXbk9LfbxugqDCwo+olqEhtPgNAUCZQGc+IBQtGV1jQkHsRfi+tgs YWVwjO3NdZuWtW2NDxsByzTuxpg7imng2HJJLeo/brhH7h+/UL0kypUy/RzGMy2N5Eq2 67GO+orU9JpwenS3aH/jx1CDQDq9rJKCEHgljVgyaampR4+Q/axwZ9tD41ZP2mu7DR0b eu04KWMZ8dV2g4b4KLh3bFF9/9iW8sDxgw23eut8XO/BCel5fOgKRHHSGi2JzqYVNUuw 8kX267XOimMQ8sDWn1R0RE7MnWme7Ie6BVzSRZ7RB/rZIQZ9M0/AgB3tGjH3Ct/K53Gj 4gNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=jkVMGHM2OFM3PfvMFosGHx1y7xB7uCorpA1+ExyeYa0=; b=dRLU2tZ8X7cLoeqLqOf0XxOgDmw9W39XI2Y5+m7mvnkj+54dxRyfOwRtEoaCsj+BDp U6gQxjf9II9bDgV4taeIpQVm5IyS9TrzCLRvjs4ESJ23OcA+IspNdtPoDRywvYh2qPym csD60m+h9H421Wh+hAsGjN/dYHVRWsUgmNAl0L6iegWwpo47ktF+eYpQzIawSfWmKPuF dGoI9nbmhbdVAIzKvUpWeq8bbuwkgdWlnS9K4WwYm4AXM+NpQayP+nNGFpCwVrRrDjPo Ag0WWUIcwLGyinXtVCouNdn4vVnqQ2WZnPZFrGk5NamkZPTZJVgsTQN/86MESYMa6vlz furw== X-Gm-Message-State: AOAM533z5lKg6mllzlVNIiJ9S7CvhP+ioQH4D2PtbRVb3DYi/0tvyl5A Z3FbwNCn63FU7Fxp/Ib40bCDPZrwfXQmUL1/liRiDA== X-Google-Smtp-Source: ABdhPJwpEoK2oZx1Gw2nZjYcFPSqZna6VwKU2kNDO2/MI2f+13r5XJtEDP3zq3xpV2Kxp/OO7rWODzigdmvO0haEREk= X-Received: by 2002:a05:6402:3548:: with SMTP id f8mr35584491edd.251.1620736916320; Tue, 11 May 2021 05:41:56 -0700 (PDT) MIME-Version: 1.0 References: <20210430202610.1136687-1-richard.henderson@linaro.org> <20210430202610.1136687-16-richard.henderson@linaro.org> In-Reply-To: <20210430202610.1136687-16-richard.henderson@linaro.org> From: Peter Maydell Date: Tue, 11 May 2021 13:40:44 +0100 Message-ID: Subject: Re: [PATCH v6 15/82] target/arm: Implement SVE2 bitwise shift left long To: Richard Henderson Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, 30 Apr 2021 at 21:41, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/helper-sve.h | 8 ++ > target/arm/sve.decode | 8 ++ > target/arm/sve_helper.c | 26 ++++++ > target/arm/translate-sve.c | 159 +++++++++++++++++++++++++++++++++++++ > 4 files changed, 201 insertions(+) > diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c > index f30f3722af..73aa670a77 100644 > --- a/target/arm/sve_helper.c > +++ b/target/arm/sve_helper.c > @@ -625,6 +625,8 @@ DO_ZPZZ(sve2_sqrshl_zpzz_h, int16_t, H1_2, do_sqrshl_h) > DO_ZPZZ(sve2_sqrshl_zpzz_s, int32_t, H1_4, do_sqrshl_s) > DO_ZPZZ_D(sve2_sqrshl_zpzz_d, int64_t, do_sqrshl_d) > > +#undef do_sqrshl_d > + > #define do_uqrshl_b(n, m) \ > ({ uint32_t discard; do_uqrshl_bhs(n, (int8_t)m, 8, true, &discard); }) > #define do_uqrshl_h(n, m) \ > @@ -639,6 +641,8 @@ DO_ZPZZ(sve2_uqrshl_zpzz_h, uint16_t, H1_2, do_uqrshl_h) > DO_ZPZZ(sve2_uqrshl_zpzz_s, uint32_t, H1_4, do_uqrshl_s) > DO_ZPZZ_D(sve2_uqrshl_zpzz_d, uint64_t, do_uqrshl_d) > > +#undef do_uqrshl_d > + > #define DO_HADD_BHS(n, m) (((int64_t)n + m) >> 1) > #define DO_HADD_D(n, m) ((n >> 1) + (m >> 1) + (n & m & 1)) These undefs look like they should be in some other patch. > +static void gen_ushll_i64(unsigned vece, TCGv_i64 d, TCGv_i64 n, int imm) > +{ > + int halfbits = 4 << vece; > + int top = imm & 1; > + int shl = (imm >> 1); > + int shift; > + uint64_t mask; > + > + mask = MAKE_64BIT_MASK(0, halfbits); > + mask <<= shl; > + mask = dup_const(vece, mask); > + > + shift = shl - top * halfbits; > + if (shift < 0) { > + tcg_gen_shri_i64(d, n, -shift); > + } else { > + tcg_gen_shri_i64(d, n, shift); Should these really both be right-shifts ? > + } > + tcg_gen_andi_i64(d, d, mask); > +} Otherwise Reviewed-by: Peter Maydell thanks -- PMM