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Fri, 11 Dec 2020 06:51:23 -0800 (PST) MIME-Version: 1.0 References: <20201208122306.8933-1-leif@nuviainc.com> <20201208122306.8933-6-leif@nuviainc.com> In-Reply-To: <20201208122306.8933-6-leif@nuviainc.com> From: Peter Maydell Date: Fri, 11 Dec 2020 14:51:11 +0000 Message-ID: Subject: Re: [PATCH 5/5] target/arm: add aarch32 ID register fields to cpu.h To: Leif Lindholm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::643; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x643.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , qemu-arm , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, 8 Dec 2020 at 12:23, Leif Lindholm wrote: > > Add entries present in ARM DDI 0487F.c (August 2020). > > Signed-off-by: Leif Lindholm > --- > target/arm/cpu.h | 37 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > FIELD(ID_MMFR4, CCIDX, 24, 4) > FIELD(ID_MMFR4, EVT, 28, 4) > > +FIELD(ID_MMFR5, ETS, 0, 4) > + > +FIELD(ID_PFR0, STATE0, 0, 4) > +FIELD(ID_PFR0, STATE1, 4, 4) > +FIELD(ID_PFR0, STATE2, 8, 4) > +FIELD(ID_PFR0, STATE3, 12, 4) > +FIELD(ID_PFR0, CSV2, 16, 4) > +FIELD(ID_PFR0, AMU, 20, 4) > +FIELD(ID_PFR0, DIT, 24, 4) > +FIELD(ID_PFR0, RAS, 28, 4) The ID_PFR0 definitions are already in master now commit 46f4976f22a45 has gone in. Otherwise Reviewed-by: Peter Maydell thanks -- PMM