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Fri, 27 Nov 2020 08:38:29 -0800 (PST) MIME-Version: 1.0 References: <20201126215017.41156-1-agraf@csgraf.de> <20201126215017.41156-9-agraf@csgraf.de> <20201126221405.GT2271382@habkost.net> <20201127162633.GY2271382@habkost.net> In-Reply-To: <20201127162633.GY2271382@habkost.net> From: Peter Maydell Date: Fri, 27 Nov 2020 16:38:18 +0000 Message-ID: Subject: Re: [PATCH 8/8] hw/arm/virt: Disable highmem when on hypervisor.framework To: Eduardo Habkost Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::643; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x643.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , QEMU Developers , Cameron Esfahani , Roman Bolshakov , Alexander Graf , Claudio Fontana , qemu-arm , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, 27 Nov 2020 at 16:26, Eduardo Habkost wrote: > > On Thu, Nov 26, 2020 at 10:29:01PM +0000, Peter Maydell wrote: > > On Thu, 26 Nov 2020 at 22:14, Eduardo Habkost wrote: > > > Direct checks for *_enabled() are a pain to clean up later when > > > we add support to new accelerators. Can't this be implemented as > > > (e.g.) a AccelClass::max_physical_address_bits field? > > > > It's a property of the CPU (eg our emulated TCG CPUs may have > > varying supported numbers of physical address bits). So the > > virt board ought to look at the CPU, and the CPU should be > > set up with the right information for all of KVM, TCG, HVF > > (either a specific max_phys_addr_bits value or just ensure > > its ID_AA64MMFR0_EL1.PARange is right, not sure which would > > be easier/nicer). > > Agreed. > > My suggestion would still apply to the CPU code that will pick > the address size; ideally, accel-specific behaviour should be > represented as meaningful fields in AccelClass (either data or > virtual methods) instead of direct *_enabled() checks. Having looked a bit more closely at some of the relevant target/arm code, I think the best approach is going to be that in virt.c we just check the PARange ID register field (probably via a convenience function that does the conversion of that to a nice number-of-bits return value; we might even have one already). KVM and TCG both already set that ID register field in the CPU struct correctly in their existing implicitly-accelerator-specific code; HVF needs to do the same. thanks -- PMM