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Thu, 20 May 2021 06:23:34 -0700 (PDT) MIME-Version: 1.0 References: <20210510190844.17799-1-peter.maydell@linaro.org> In-Reply-To: <20210510190844.17799-1-peter.maydell@linaro.org> From: Peter Maydell Date: Thu, 20 May 2021 14:23:16 +0100 Message-ID: Subject: Re: [PATCH 0/6] hw/arm: Fix modelling of SSE-300 TCMs and SRAM To: qemu-arm , QEMU Developers Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kumar Gala , Jimmy Brisson , Kevin Townsend , Devaraj Ranganna Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, 10 May 2021 at 20:08, Peter Maydell wrote: > > This patchset fixes some bugs in how we were modelling the > TCMs and the SRAM in the SSE-300 which were preventing > Arm TF-M from booting on our AN547 model; there are also > some fixes to things I noticed while I was in the code. > > The specific bugs preventing boot were: > * SRAM_ADDR_WIDTH for the AN547 is 21, not 15, so the SRAM > area was too small > * we were putting the SRAMs at the wrong address (0x2100_0000 > for SSE-300, not 0x2000_0000 as for SSE-200) > > The other stuff I've fixed is: > * we were modelling the SRAM in the AN524 both in the SSE > and in the board model (harmlessly, as the board-model > memory was just always shadowed in the memory map and > unreachable) > * we were modelling the TCMs in the AN547 board model, > which is conceptually wrong because in hardware they're > part of the SSE-300. No guest-visible change, but it will > avoid problems if/when we add another SSE-300 board model > > thanks > -- PMM Ping for code review, please? thanks -- PMM