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Mon, 08 Mar 2021 02:10:00 -0800 (PST) MIME-Version: 1.0 References: <20210305135451.15427-1-alex.bennee@linaro.org> <20210305135451.15427-4-alex.bennee@linaro.org> <87im65gxla.fsf@keithp.com> <877dmlgnrf.fsf@keithp.com> <87o8fwfcjd.fsf@keithp.com> In-Reply-To: <87o8fwfcjd.fsf@keithp.com> From: Peter Maydell Date: Mon, 8 Mar 2021 10:09:44 +0000 Message-ID: Subject: Re: [PATCH v1 3/3] semihosting/arg-compat: fix up handling of SYS_HEAPINFO To: Keith Packard Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bug 1915925 <1915925@bugs.launchpad.net>, "open list:ARM TCG CPUs" , =?UTF-8?B?QWxleCBCZW5uw6ll?= , QEMU Developers , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Sat, 6 Mar 2021 at 16:54, Keith Packard wrote: > > Peter Maydell writes: > > Part of why I asked is that the current RISCV implementation > > is just looking at sizeof(target_ulong); but the qemu-system-riscv64 > > executable AIUI now supports emulating both "this is a 64 bit > > guest CPU" and "this is a 32 bit host CPU", and so looking at > > a QEMU-compile-time value like "sizeof(target_ulong)" will > > produce the wrong answer for 32-bit CPUs emulated in > > the qemu-system-riscv64 binary. My guess is maybe > > it should be looking at the result of riscv_cpu_is_32bit() instead. > > Wow. I read through the code and couldn't find anything that looked like > it supported that, sounds like I must have missed something? I thought Alistair had done that work (which brings riscv into line with the other 32/64 bit QEMU targets, which all support the 32-bit CPU types in the 64-bit-capable executable). But maybe it hasn't landed in master yet? thanks -- PMM From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57A07C433DB for ; Mon, 8 Mar 2021 10:16:47 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8401C6510E for ; Mon, 8 Mar 2021 10:16:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8401C6510E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bugs.launchpad.net Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:35752 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lJCwP-0003DP-Hw for qemu-devel@archiver.kernel.org; Mon, 08 Mar 2021 05:16:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36498) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lJCvQ-0002fF-LP for qemu-devel@nongnu.org; Mon, 08 Mar 2021 05:15:45 -0500 Received: from indium.canonical.com ([91.189.90.7]:48302) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lJCvK-00084M-Vl for qemu-devel@nongnu.org; Mon, 08 Mar 2021 05:15:44 -0500 Received: from loganberry.canonical.com ([91.189.90.37]) by indium.canonical.com with esmtp (Exim 4.86_2 #2 (Debian)) id 1lJCvI-0005mW-Sk for ; Mon, 08 Mar 2021 10:15:36 +0000 Received: from loganberry.canonical.com (localhost [127.0.0.1]) by loganberry.canonical.com (Postfix) with ESMTP id D14412E815C for ; Mon, 8 Mar 2021 10:15:36 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Date: Mon, 08 Mar 2021 10:09:44 -0000 From: Peter Maydell <1915925@bugs.launchpad.net> To: qemu-devel@nongnu.org X-Launchpad-Notification-Type: bug X-Launchpad-Bug: product=qemu; status=Confirmed; importance=Undecided; assignee=alex.bennee@linaro.org; X-Launchpad-Bug-Tags: semihosting testcase X-Launchpad-Bug-Information-Type: Public X-Launchpad-Bug-Private: no X-Launchpad-Bug-Security-Vulnerability: no X-Launchpad-Bug-Commenters: ajbennee inver7 keithp pmaydell X-Launchpad-Bug-Reporter: iNvEr7 (inver7) X-Launchpad-Bug-Modifier: Peter Maydell (pmaydell) References: <161356438332.24036.4652954745285513495.malonedeb@chaenomeles.canonical.com> <20210305135451.15427-4-alex.bennee@linaro.org> <87im65gxla.fsf@keithp.com> <877dmlgnrf.fsf@keithp.com> <87o8fwfcjd.fsf@keithp.com> Message-ID: Subject: [Bug 1915925] Re: [PATCH v1 3/3] semihosting/arg-compat: fix up handling of SYS_HEAPINFO X-Launchpad-Message-Rationale: Subscriber (QEMU) @qemu-devel-ml X-Launchpad-Message-For: qemu-devel-ml Precedence: bulk X-Generated-By: Launchpad (canonical.com); Revision="fc09074b06b3b9178bd28175bdab646b3b5abfce"; Instance="production" X-Launchpad-Hash: 355c51b82f16af3f63b1737de06bb952c57d2b43 Received-SPF: none client-ip=91.189.90.7; envelope-from=bounces@canonical.com; helo=indium.canonical.com X-Spam_score_int: -66 X-Spam_score: -6.7 X-Spam_bar: ------ X-Spam_report: (-6.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Bug 1915925 <1915925@bugs.launchpad.net> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Message-ID: <20210308100944.v1zragrpLbtlLgLIJid2afPPMVcePI2wH41Ss4CJoAk@z> On Sat, 6 Mar 2021 at 16:54, Keith Packard wrote: > > Peter Maydell writes: > > Part of why I asked is that the current RISCV implementation > > is just looking at sizeof(target_ulong); but the qemu-system-riscv64 > > executable AIUI now supports emulating both "this is a 64 bit > > guest CPU" and "this is a 32 bit host CPU", and so looking at > > a QEMU-compile-time value like "sizeof(target_ulong)" will > > produce the wrong answer for 32-bit CPUs emulated in > > the qemu-system-riscv64 binary. My guess is maybe > > it should be looking at the result of riscv_cpu_is_32bit() instead. > > Wow. I read through the code and couldn't find anything that looked like > it supported that, sounds like I must have missed something? I thought Alistair had done that work (which brings riscv into line with the other 32/64 bit QEMU targets, which all support the 32-bit CPU types in the 64-bit-capable executable). But maybe it hasn't landed in master yet? thanks -- PMM -- = You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1915925 Title: ARM semihosting HEAPINFO results wrote to wrong address Status in QEMU: Confirmed Bug description: This affects latest development branch of QEMU. According to the ARM spec of the HEAPINFO semihosting call: https://developer.arm.com/documentation/100863/0300/Semihosting- operations/SYS-HEAPINFO--0x16-?lang=3Den > the PARAMETER REGISTER contains the address of a pointer to a four- field data block. However, QEMU treated the PARAMETER REGISTER as pointing to a four- field data block directly. Here is a simple program that can demonstrate this problem: https://github.com/iNvEr7/qemu-learn/tree/newlib-bug/semihosting- newlib This code links with newlib with semihosting mode, which will call the HEAPINFO SVC during crt0 routine. When running in QEMU (make run), it may crash the program either because of invalid write or memory curruption, depending on the compiled program structure. Also refer to my discussion with newlib folks: https://sourceware.org/pipermail/newlib/2021/018260.html To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1915925/+subscriptions