From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42910) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VsUc6-00050J-8D for qemu-devel@nongnu.org; Mon, 16 Dec 2013 04:37:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VsUc1-0004AH-2x for qemu-devel@nongnu.org; Mon, 16 Dec 2013 04:37:22 -0500 Received: from mail-pd0-f176.google.com ([209.85.192.176]:46222) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VsUc0-00049V-U0 for qemu-devel@nongnu.org; Mon, 16 Dec 2013 04:37:17 -0500 Received: by mail-pd0-f176.google.com with SMTP id w10so5108518pde.7 for ; Mon, 16 Dec 2013 01:37:16 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <52AEBFCD.9090007@huawei.com> References: <1386962282-6839-1-git-send-email-peter.maydell@linaro.org> <1386962282-6839-8-git-send-email-peter.maydell@linaro.org> <52AEBFCD.9090007@huawei.com> From: Peter Maydell Date: Mon, 16 Dec 2013 09:36:56 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v3 7/8] target-arm: A64: add support for 3 src data proc insns List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Claudio Fontana Cc: Laurent Desnogues , Patch Tracking , Michael Matz , QEMU Developers , Claudio Fontana , Dirk Mueller , Will Newton , =?UTF-8?B?QWxleCBCZW5uw6ll?= , "kvmarm@lists.cs.columbia.edu" , Christoffer Dall , Richard Henderson On 16 December 2013 08:54, Claudio Fontana wro= te: > Hello Peter, > > On 13.12.2013 20:18, Peter Maydell wrote: >> From: Alexander Graf >> >> This patch adds emulation for the "Data-processing (3 source)" >> family of instructions, namely MADD, MSUB, SMADDL, SMSUBL, SMULH, >> UMADDL, UMSUBL, UMULH. >> >> Signed-off-by: Alexander Graf >> Signed-off-by: Alex Benn=C3=A9e >> Signed-off-by: Peter Maydell >> --- >> target-arm/translate-a64.c | 91 +++++++++++++++++++++++++++++++++++++++= ++++++- >> 1 file changed, 89 insertions(+), 2 deletions(-) >> >> diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c >> index a6f1945..b3e9449 100644 >> --- a/target-arm/translate-a64.c >> +++ b/target-arm/translate-a64.c >> @@ -2125,10 +2125,97 @@ static void disas_add_sub_reg(DisasContext *s, u= int32_t insn) >> tcg_temp_free_i64(tcg_result); >> } >> >> -/* Data-processing (3 source) */ >> +/* C3.5.9 Data-processing (3 source) >> + >> + 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0 >> + +--+------+-----------+------+------+----+------+------+------+ >> + |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd | >> + +--+------+-----------+------+------+----+------+------+------+ >> + >> + */ >> static void disas_data_proc_3src(DisasContext *s, uint32_t insn) >> { >> - unsupported_encoding(s, insn); >> + int rd =3D extract32(insn, 0, 5); >> + int rn =3D extract32(insn, 5, 5); >> + int ra =3D extract32(insn, 10, 5); >> + int rm =3D extract32(insn, 16, 5); >> + int op_id =3D (extract32(insn, 29, 3) << 4) | >> + (extract32(insn, 21, 3) << 1) | >> + extract32(insn, 15, 1); >> + bool is_32bit =3D !extract32(insn, 31, 1); > > we have used "sf" everywhere else.. Yes, might as well be consistent. >> + tcg_temp_free(low_bits); > > should this be tcg_temp_free_i64()? Yes, since we're preferring to be explicit about i32 vs i64 temps. (We know we're always building a 64 bit binary for translate-a64.c so in fact we can guarantee that tcg_temp_free is always tcg_temp_free_i64; but consistency with the 32 bit decoder is nice.) Fixed these nits in my working tree. thanks -- PMM