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From: Peter Maydell <peter.maydell@linaro.org>
Date: Thu, 28 Jun 2018 15:55:10 +0100
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Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH v6 00/35] target/arm SVE patches
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To: =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>
Cc: Richard Henderson <richard.henderson@linaro.org>, QEMU Developers <qemu-devel@nongnu.org>, qemu-arm <qemu-arm@nongnu.org>

On 28 June 2018 at 15:12, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 28 June 2018 at 12:30, Alex Benn=C3=A9e <alex.bennee@linaro.org> wrote=
:
>>   loading test image
>>   sve-all-short-v8.3+sve@vq3/insn_sdiv_z_p_zz___INC.risu.bin...
>>   starting apprentice image at 0x4000801000
>>   starting image
>>   fish: =E2=80=9C../qemu.git/aarch64-linux-user/=E2=80=A6=E2=80=9D termi=
nated by signal SIGFPE
>>   (Floating point exception)
>
> Do you have the insn that it's barfing on? In particular,
> I'm guessing from the test name that this is for something
> covered by one of the SDIV_zpzz lines in sve.decode, which
> is already in master rather than in this test series.
> If that's true, then it shouldn't block applying this set...

Further discussion on IRC suggests that this is failing on
MININT idiv -1, which is an annoying special case that x86
happens to generate SIGFPE for. Compare our HELPER(sdiv) code:

int32_t HELPER(sdiv)(int32_t num, int32_t den)
{
    if (den =3D=3D 0)
      return 0;
    if (num =3D=3D INT_MIN && den =3D=3D -1)
      return INT_MIN;
    return num / den;
}

with what we do for SVE:

#define DO_DIV(N, M)  (M ? N / M : 0)

This is OK for unsigned division, but signed division needs to
special case INT_MIN / -1.

In any case, this is in an existing insn, so I'm going to apply
this series to target-arm.next (fixing up the patch 5 comment
typo).

thanks
-- PMM