From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:34239) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ReG8O-0003PS-W5 for qemu-devel@nongnu.org; Fri, 23 Dec 2011 20:10:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ReG8N-0002sX-Kl for qemu-devel@nongnu.org; Fri, 23 Dec 2011 20:10:48 -0500 Received: from mail-qy0-f173.google.com ([209.85.216.173]:47611) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ReG8N-0002sT-A2 for qemu-devel@nongnu.org; Fri, 23 Dec 2011 20:10:47 -0500 Received: by qcsd15 with SMTP id d15so6303597qcs.4 for ; Fri, 23 Dec 2011 17:10:46 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <4EF522CA.4040106@calxeda.com> References: <1324578014-24746-1-git-send-email-mark.langsdorf@calxeda.com> <1324578014-24746-10-git-send-email-mark.langsdorf@calxeda.com> <4EF522CA.4040106@calxeda.com> Date: Sat, 24 Dec 2011 01:10:46 +0000 Message-ID: From: Peter Maydell Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 9/9] arm: increase a9mp interrupts to 160 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Rob Herring Cc: kwolf@redhat.com, qemu-devel@nongnu.org, Mark Langsdorf , paul@codesourcery.com On 24 December 2011 00:54, Rob Herring wrote: > Mark, > > On 12/22/2011 12:20 PM, Mark Langsdorf wrote: >> From: Rob Herring >> >> Signed-off-by: Rob Herring >> Signed-off-by: Mark Langsdorf >> --- >> =C2=A0hw/a9mpcore.c | =C2=A0 =C2=A02 +- >> =C2=A01 files changed, 1 insertions(+), 1 deletions(-) >> >> diff --git a/hw/a9mpcore.c b/hw/a9mpcore.c >> index 875ae98..93b0498 100644 >> --- a/hw/a9mpcore.c >> +++ b/hw/a9mpcore.c >> @@ -13,7 +13,7 @@ >> =C2=A0/* Configuration for arm_gic.c: >> =C2=A0 * number of external IRQ lines, max number of CPUs, how to ID cur= rent CPU >> =C2=A0 */ >> -#define GIC_NIRQ 96 >> +#define GIC_NIRQ 160 >> =C2=A0#define NCPU 4 > > This needs to be run-time. The value gets put in a register and read by > the OS. It breaks platforms expecting 96 irqs. Also the hardware maximum for the A9 is 256, so bumping the compile time maximum to only 160 wouldn't make sense. (The GIC architectural limit is 1020 interrupts.) FYI: In the long term the place I would like to get to is to have the GIC be a properly separated out qdev device, rather than a bit of code which is #included by various different source files which do this kind of compile-time configuration for it. Having the private peripheral qdev devices be subclasses of the GIC is also a bit of a workaround for limitations of our current device object model which I hope QOM will let us rearrange. -- PMM