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From: Peter Maydell <peter.maydell@linaro.org>
Date: Wed, 21 Oct 2015 13:24:30 +0100
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Content-Type: text/plain; charset=UTF-8
Subject: Re: [Qemu-devel] [PATCH RFC V5 9/9] hw/arm: Add virt-v3 machine
	that uses GIC-500
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To: Shlomo Pongratz <shlomopongratz@gmail.com>
Cc: "eric.auger@linaro.org" <eric.auger@linaro.org>, Shlomo Pongratz <shlomo.pongratz@huawei.com>, Pavel Fedin <p.fedin@samsung.com>, "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>, "shannon.zhao@linaro.org" <shannon.zhao@linaro.org>, "ashoks@broadcom.com" <ashoks@broadcom.com>, "imammedo@redhat.com" <imammedo@redhat.com>

On 21 October 2015 at 12:33, Shlomo Pongratz <shlomopongratz@gmail.com> wrote:
> I assume I can add the system registers to target-arm/cpu.c but I wonder if
> someone really needs to simulate more than 8 AArch32 CPU(s)

The system register implementation belongs in the gic code, not
target-arm/. We already have support for devices that say
"I have some system registers, please add them to this CPU".

The mechanism is the same for system registers for both 32-bit
and 64-bit, incidentally.

thanks
-- PMM