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From: Peter Maydell <peter.maydell@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>, qemu-arm <qemu-arm@nongnu.org>
Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH 4/9] tcg: Introduce atomic helpers for integer min/max
Date: Thu, 3 May 2018 14:26:17 +0100	[thread overview]
Message-ID: <CAFEAcA-wq3kasUe8pkdUJXNJYNnLABrPgeQE4fokSLL995SFkg@mail.gmail.com> (raw)
In-Reply-To: <20180427002651.28356-5-richard.henderson@linaro.org>

On 27 April 2018 at 01:26, Richard Henderson
<richard.henderson@linaro.org> wrote:
> Given that this atomic operation will be used by both risc-v
> and aarch64, let's not duplicate code across the two targets.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  accel/tcg/atomic_template.h | 71 +++++++++++++++++++++++++++++++++++++++++++++
>  accel/tcg/tcg-runtime.h     |  8 +++++
>  tcg/tcg-op.h                | 34 ++++++++++++++++++++++
>  tcg/tcg.h                   |  8 +++++
>  tcg/tcg-op.c                |  8 +++++
>  5 files changed, 129 insertions(+)

> @@ -233,6 +270,39 @@ ABI_TYPE ATOMIC_NAME(add_fetch)(CPUArchState *env, target_ulong addr,
>          ldo = ldn;
>      }
>  }
> +
> +/* These helpers are, as a whole, full barriers.  Within the helper,
> + * the leading barrier is explicit and the trailing barrier is within
> + * cmpxchg primitive.
> + */
> +#define GEN_ATOMIC_HELPER_FN(X, FN, XDATA_TYPE, RET)                \
> +ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr,       \
> +                        ABI_TYPE xval EXTRA_ARGS)                   \
> +{                                                                   \
> +    ATOMIC_MMU_DECLS;                                               \
> +    XDATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;                          \
> +    XDATA_TYPE ldo, ldn, old, new, val = xval;                      \
> +    smp_mb();                                                       \
> +    ldn = atomic_read__nocheck(haddr);                              \

I see you're using the __nocheck function here. How does this
work for the 32-bit host case where you don't necessarily have
a 64-bit atomic primitive?

> +    do {                                                            \
> +        ldo = ldn; old = BSWAP(ldo); new = FN(old, val);            \
> +        ldn = atomic_cmpxchg__nocheck(haddr, ldo, BSWAP(new));      \
> +    } while (ldo != ldn);                                           \
> +    ATOMIC_MMU_CLEANUP;                                             \
> +    return RET;                                                     \
> +}

I was going to suggest that you could also now use this to
iimplement the currently-hand-coded fetch_add and add_fetch
for the reverse-host-endian case, but those don't have a leading
smp_mb() and this does. Do you know why those are different?

thanks
-- PMM

  reply	other threads:[~2018-05-03 13:26 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-27  0:26 [Qemu-devel] [PATCH 0/9] target/arm: Implement v8.1-Atomics Richard Henderson
2018-04-27  0:26 ` [Qemu-devel] [PATCH 1/9] tcg: Introduce helpers for integer min/max Richard Henderson
2018-05-03 13:10   ` [Qemu-devel] [Qemu-arm] " Peter Maydell
2018-04-27  0:26 ` [Qemu-devel] [PATCH 2/9] target/arm: Use new min/max expanders Richard Henderson
2018-05-03 13:14   ` [Qemu-devel] [Qemu-arm] " Peter Maydell
2018-04-27  0:26 ` [Qemu-devel] [PATCH 3/9] target/xtensa: " Richard Henderson
2018-04-27 15:06   ` Max Filippov
2018-04-27  0:26 ` [Qemu-devel] [PATCH 4/9] tcg: Introduce atomic helpers for integer min/max Richard Henderson
2018-05-03 13:26   ` Peter Maydell [this message]
2018-05-03 17:13     ` [Qemu-devel] [Qemu-arm] " Richard Henderson
2018-05-03 17:26       ` Peter Maydell
2018-05-03 17:39         ` Richard Henderson
2018-05-03 18:19           ` Peter Maydell
2018-04-27  0:26 ` [Qemu-devel] [PATCH 5/9] target/riscv: Use new atomic min/max expanders Richard Henderson
2018-04-27  7:24   ` Michael Clark
2018-04-27 17:53     ` Richard Henderson
2018-04-29 23:03       ` Michael Clark
2018-04-27  0:26 ` [Qemu-devel] [PATCH 6/9] target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decode Richard Henderson
2018-05-03 13:59   ` Peter Maydell
2018-05-03 14:26     ` Peter Maydell
2018-04-27  0:26 ` [Qemu-devel] [PATCH 7/9] target/arm: Fill in disas_ldst_atomic Richard Henderson
2018-05-03 14:14   ` [Qemu-devel] [Qemu-arm] " Peter Maydell
2018-05-03 17:18     ` Richard Henderson
2018-04-27  0:26 ` [Qemu-devel] [PATCH 8/9] target/arm: Implement CAS and CASP Richard Henderson
2018-05-03 14:55   ` Peter Maydell
2018-05-03 17:32     ` Richard Henderson
2018-05-04 16:06       ` Peter Maydell
2018-04-27  0:26 ` [Qemu-devel] [PATCH 9/9] target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only Richard Henderson
2018-05-03 14:26   ` [Qemu-devel] [Qemu-arm] " Peter Maydell
2018-04-27  0:53 ` [Qemu-devel] [PATCH 0/9] target/arm: Implement v8.1-Atomics no-reply

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