From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54107) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WYMLO-0000YD-G2 for qemu-devel@nongnu.org; Thu, 10 Apr 2014 17:17:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WYMLJ-0001Xa-MX for qemu-devel@nongnu.org; Thu, 10 Apr 2014 17:17:10 -0400 Received: from mail-la0-f54.google.com ([209.85.215.54]:63639) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WYMLJ-0001XR-FC for qemu-devel@nongnu.org; Thu, 10 Apr 2014 17:17:05 -0400 Received: by mail-la0-f54.google.com with SMTP id mc6so2827177lab.13 for ; Thu, 10 Apr 2014 14:17:04 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: <1394134385-1727-1-git-send-email-peter.maydell@linaro.org> <1394134385-1727-22-git-send-email-peter.maydell@linaro.org> From: Peter Maydell Date: Thu, 10 Apr 2014 22:16:44 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH v4 21/21] hw/arm/virt: Add support for Cortex-A57 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Rob Herring Cc: Rob Herring , Peter Crosthwaite , Patch Tracking , Michael Matz , "qemu-devel@nongnu.org Developers" , Will Newton , Dirk Mueller , Laurent Desnogues , "kvmarm@lists.cs.columbia.edu" , Richard Henderson On 10 April 2014 20:41, Rob Herring wrote: > On Thu, Apr 10, 2014 at 10:02 AM, Peter Maydell > wrote: >> We could in theory write an a57mpcore_priv which was a >> carbon copy of a15mpcore_priv, but that seems a bit pointless. >> I think it's probably actually reasonable to use a15mpcore_priv >> here, with an appropriate comment: >> >> /* Our A57 has an A15-style GICv2, so we can use a15mpcore_priv */ > > I think there are 3 possibilities of what actual h/w may look like. i > agree this is the correct thing to do for one case (and is the only > one qemu is able to support today). The others are: > > A57 + SBSA compliant GICv2(M) > A57 + GICv3 > > The SBSA change is making each register bank within the GIC 64K spaced > instead of 4K spaced to support 64KB pages in OSs and hypervisors. That part is pretty easy to do in QEMU -- we'd just need a suitable container object that mapped the GIC regions in different locations. It might be worth doing that now rather than putting this in and then changing it later. > This is a simple address swizzling trick defined in the SBSA doc. > (Since it's documented it must not be a cute embedded nonsense hack. > :)) Then the M portion is for PCI MSI support which is optional. I haven't looked too closely at the GICv2M spec but it probably is not too hard (certainly in comparison to the v3 GIC ;-)) thanks -- PMM