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From: Peter Maydell <peter.maydell@linaro.org>
To: Jinjie Ruan <ruanjinjie@huawei.com>
Cc: eduardo@habkost.net, marcel.apfelbaum@gmail.com,
	philmd@linaro.org,  wangyanan55@huawei.com,
	richard.henderson@linaro.org, qemu-devel@nongnu.org,
	 qemu-arm@nongnu.org
Subject: Re: [PATCH v10 18/23] hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read()
Date: Thu, 28 Mar 2024 19:27:10 +0000	[thread overview]
Message-ID: <CAFEAcA80e7j+euG9Fqtx5j-BnGMoK-bGoPrfFqfokJQE-kCcUA@mail.gmail.com> (raw)
In-Reply-To: <20240325084854.3010562-19-ruanjinjie@huawei.com>

On Mon, 25 Mar 2024 at 08:52, Jinjie Ruan <ruanjinjie@huawei.com> wrote:
>
> Implement icv_nmiar1_read() for icc_nmiar1_read(), so add definition for
> ICH_LR_EL2.NMI and ICH_AP1R_EL2.NMI bit.
>
> If FEAT_GICv3_NMI is supported, ich_ap_write() should consider ICV_AP1R_EL1.NMI
> bit. In icv_activate_irq() and icv_eoir_write(), the ICV_AP1R_EL1.NMI bit
> should be set or clear according to the Non-maskable property. And the RPR
> priority should also update the NMI bit according to the APR priority NMI bit.
>
> By the way, add gicv3_icv_nmiar1_read trace event.
>
> If the hpp irq is a NMI, the icv iar read should return 1022 and trap for
> NMI again
>
> Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> v10:
> - Rename ICH_AP1R_EL2_NMI to ICV_AP1R_EL1_NMI.
> - Add ICV_RPR_EL1_NMI definition.
> - Set ICV_RPR_EL1.NMI according to the ICV_AP1R<n>_EL1.NMI in
>   ich_highest_active_virt_prio().
> v9:
> - Correct the INTID_NMI logic.
> v8:
> - Fix an unexpected interrupt bug when sending VNMI by running qemu VM.
> v7:
> - Add Reviewed-by.
> v6:
> - Implement icv_nmiar1_read().
> ---
>  hw/intc/arm_gicv3_cpuif.c | 79 +++++++++++++++++++++++++++++++++------
>  hw/intc/gicv3_internal.h  |  4 ++
>  hw/intc/trace-events      |  1 +
>  3 files changed, 73 insertions(+), 11 deletions(-)

I haven't done a full review of this yet, but it looks like some of
the parts that applied to physical interrupts apply here too, eg
 * don't do the RPR NMI bit handling in ich_highest_active_virt_prio(),
   deal with NMI in the callers
 * in the AP registers, set either NMI or a group-priority bit, not both
 * AP NMI bits are only in the 0 reg, so checking doesn't need to be
   inside the for loop

You'll also need to update hppvi_index() so it accounts for NMIs
when it's finding the highest priority interrupt in the list registers:
compare the HighestPriorityVirtualInterrupt() pseudocode function.

thanks
-- PMM


  reply	other threads:[~2024-03-28 19:27 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-25  8:48 [PATCH v10 00/23] target/arm: Implement FEAT_NMI and FEAT_GICv3_NMI Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 01/23] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 02/23] target/arm: Add PSTATE.ALLINT Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 03/23] target/arm: Add support for FEAT_NMI, Non-maskable Interrupt Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 04/23] target/arm: Implement ALLINT MSR (immediate) Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 05/23] target/arm: Support MSR access to ALLINT Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 06/23] target/arm: Add support for Non-maskable Interrupt Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 07/23] target/arm: Add support for NMI in arm_phys_excp_target_el() Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 08/23] target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 09/23] target/arm: Handle PSTATE.ALLINT on taking an exception Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 10/23] hw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPU Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 11/23] hw/intc/arm_gicv3: Add external IRQ lines for NMI Jinjie Ruan via
2024-03-28 14:55   ` Peter Maydell
2024-03-25  8:48 ` [PATCH v10 12/23] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64() Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 13/23] hw/intc: Enable FEAT_GICv3_NMI Feature Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 14/23] hw/intc/arm_gicv3: Add irq non-maskable property Jinjie Ruan via
2024-03-28 14:54   ` Peter Maydell
2024-03-30  1:42     ` Jinjie Ruan via
2024-03-30 14:45       ` Peter Maydell
2024-03-25  8:48 ` [PATCH v10 15/23] hw/intc/arm_gicv3_redist: Implement GICR_INMIR0 Jinjie Ruan via
2024-03-28 14:56   ` Peter Maydell
2024-03-25  8:48 ` [PATCH v10 16/23] hw/intc/arm_gicv3: Implement GICD_INMIR Jinjie Ruan via
2024-03-28 14:57   ` Peter Maydell
2024-03-25  8:48 ` [PATCH v10 17/23] hw/intc/arm_gicv3: Add NMI handling CPU interface registers Jinjie Ruan via
2024-03-28 14:50   ` Peter Maydell
2024-03-30  2:44     ` Jinjie Ruan via
2024-03-30 14:48       ` Peter Maydell
2024-03-25  8:48 ` [PATCH v10 18/23] hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read() Jinjie Ruan via
2024-03-28 19:27   ` Peter Maydell [this message]
2024-03-25  8:48 ` [PATCH v10 19/23] hw/intc/arm_gicv3: Implement NMI interrupt prioirty Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 20/23] hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update() Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 21/23] hw/intc/arm_gicv3: Report the VINMI interrupt Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 22/23] target/arm: Add FEAT_NMI to max Jinjie Ruan via
2024-03-25  8:48 ` [PATCH v10 23/23] hw/arm/virt: Add FEAT_GICv3_NMI feature support in virt GIC Jinjie Ruan via

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