From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54367) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYWtT-0003UA-VA for qemu-devel@nongnu.org; Thu, 28 Jun 2018 09:23:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYWtS-0003Or-VH for qemu-devel@nongnu.org; Thu, 28 Jun 2018 09:23:27 -0400 Received: from mail-ot0-x242.google.com ([2607:f8b0:4003:c0f::242]:45823) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYWtS-0003Nw-Q0 for qemu-devel@nongnu.org; Thu, 28 Jun 2018 09:23:26 -0400 Received: by mail-ot0-x242.google.com with SMTP id k3-v6so6083109otl.12 for ; Thu, 28 Jun 2018 06:23:26 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <50e46f22-1e3d-10ce-5b5b-a10af49a95f1@vivier.eu> References: <20180626165658.31394-1-peter.maydell@linaro.org> <20180626165658.31394-24-peter.maydell@linaro.org> <50e46f22-1e3d-10ce-5b5b-a10af49a95f1@vivier.eu> From: Peter Maydell Date: Thu, 28 Jun 2018 14:23:05 +0100 Message-ID: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PULL 23/32] tcg: Support MMU protection regions smaller than TARGET_PAGE_SIZE List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Laurent Vivier Cc: QEMU Developers On 28 June 2018 at 14:03, Laurent Vivier wrote: > Le 26/06/2018 =C3=A0 18:56, Peter Maydell a =C3=A9crit : >> Add support for MMU protection regions that are smaller than >> TARGET_PAGE_SIZE. We do this by marking the TLB entry for those >> pages with a flag TLB_RECHECK. This flag causes us to always >> take the slow-path for accesses. In the slow path we can then >> special case them to always call tlb_fill() again, so we have >> the correct information for the exact address being accessed. >> >> This change allows us to handle reading and writing from small >> regions; we cannot deal with execution from the small region. >> >> Signed-off-by: Peter Maydell >> Reviewed-by: Richard Henderson >> Message-id: 20180620130619.11362-2-peter.maydell@linaro.org >> --- >> accel/tcg/softmmu_template.h | 24 ++++--- >> include/exec/cpu-all.h | 5 +- >> accel/tcg/cputlb.c | 131 +++++++++++++++++++++++++++++------ >> 3 files changed, 130 insertions(+), 30 deletions(-) > > This patch breaks Quadra 800 emulation, any idea why? > > ABCFGHIJK > qemu: fatal: Unable to handle guest executing from RAM within a small > MPU region at 0x0014cb5a Hmm, that shouldn't happen unless your target code was incorrectly returning a too-small page size. (I say "incorrectly" because before this patchseries that was unsupported and would have had weird effects depending on exactly what the order of guest accesses to the page was.) You could look at whether the m68k code is calling tlb_set_page() with a wrong page_size value and why that happens. You can get back the old behaviour by having your code do if (page_size < TARGET_PAGE_SIZE) { page_size =3D TARGET_PAGE_SIZE; } but that is definitely a bit of a hack. Does the m68k MMU let you specify permissions and mappings for sub-page sizes ? I do notice an oddity: in m68k_cpu_handle_mmu_fault() we call get_physical_address() but then ignore the page_size it returns when we call tlb_set_page() and instead use TARGET_PAGE_SIZE. But in the ptest helper function we use the page_size from get_physical_address() directly. Are these bits of code deliberately different? In fact it's not clear to me at all that PTEST should be updating the QEMU TLB: it only needs to update the MMU status registers. (The 68030 manual I have says that in hardware PTEST doesn't update the ATC, which is the h/w equivalent to doing a TLB update.) thanks -- PMM