From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41315) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YEh39-0005An-RU for qemu-devel@nongnu.org; Fri, 23 Jan 2015 11:25:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YEh34-0006SS-Lo for qemu-devel@nongnu.org; Fri, 23 Jan 2015 11:25:35 -0500 Received: from mail-la0-f47.google.com ([209.85.215.47]:50831) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YEh34-0006SE-DU for qemu-devel@nongnu.org; Fri, 23 Jan 2015 11:25:30 -0500 Received: by mail-la0-f47.google.com with SMTP id hz20so8185284lab.6 for ; Fri, 23 Jan 2015 08:25:29 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <1422029835-4696-2-git-send-email-greg.bellows@linaro.org> References: <1422029835-4696-1-git-send-email-greg.bellows@linaro.org> <1422029835-4696-2-git-send-email-greg.bellows@linaro.org> From: Peter Maydell Date: Fri, 23 Jan 2015 16:25:09 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH V2 1/4] target-arm: Fix RVBAR_EL1 register encoding List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Greg Bellows Cc: QEMU Developers On 23 January 2015 at 16:17, Greg Bellows wrote: > Fix the RVBAR_EL1 CP register opc2 encoding from 2 to 1 > > Signed-off-by: Greg Bellows > --- > target-arm/helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 1a5e067..c9b1c08 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -3055,7 +3055,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) > }; > ARMCPRegInfo rvbar = { > .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, > - .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2, > + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, > .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar > }; > define_one_arm_cp_reg(cpu, &rvbar); > -- Reviewed-by: Peter Maydell thanks -- PMM