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Date: Thu, 22 Dec 2011 12:30:56 +0000
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From: Peter Maydell <peter.maydell@linaro.org>
Content-Type: text/plain; charset=UTF-8
Subject: Re: [Qemu-devel] [PATCH v4 04/11] ARM: exynos4210: IRQ subsystem
	support.
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To: Evgeny Voevodin <e.voevodin@samsung.com>
Cc: m.kozlov@samsung.com, qemu-devel@nongnu.org, d.solodkiy@samsung.com

On 22 December 2011 07:03, Evgeny Voevodin <e.voevodin@samsung.com> wrote:
> Second GIC (external) is represented as "exynos4210.gic" with splitted
> mapping for CPU (0x10480000) and Distributer (0x10490000) (we used
> arm_gic.c availability to split CPU and Distributer memories).
>
> The reason for creation of this device with it's own read/write functions
> is:
>
> CPU and Distributer registers which are banked per SMP Core in internal GIC
> are not banked in external GIC and their offsets could not be used as is
> with arm_gic.c.
> External GIC registers in comparison to Internal GIC registers are moved
> from base by offset n * 0x8000 for each SMP Core, where n is SMP Core index.

Right, so just map each of the memory regions arm_gic exposes for
core 0, core 1, ... to these addresses, and don't map the memory
region corresponding to "CPU interface for this core" at all.

-- PMM