[PATCH 0/4] target/arm: SVE fixes versus VHE

[PATCH 0/4] target/arm: SVE fixes versus VHE

[Richard Henderson]

Fix two problems described in

https://lore.kernel.org/qemu-devel/6cdfd5de-2465-adca-73b3-9c66945cf18a@huawei.com/

with some other minor code cleanup.


r~


Richard Henderson (4):
  target/arm: Fix sve_zcr_len_for_el for VHE mode running
  target/arm: Tidy sve_exception_el for CPACR_EL1 access
  target/arm: Fix {fp,sve}_exception_el for VHE mode running
  target/arm: Use CPTR_TFP with CPTR_EL3 in fp_exception_el

 target/arm/helper.c | 118 ++++++++++++++++++++++++++++++--------------
 1 file changed, 80 insertions(+), 38 deletions(-)

-- 
2.25.1

[PATCH 1/4] target/arm: Fix sve_zcr_len_for_el for VHE mode running

[Richard Henderson]

When HCR_EL2.{E2H,TGE} == '11', ZCR_EL1 is unused.

Reported-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/helper.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index cfca0f5ba6..d9ee2ba5f4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6225,7 +6225,8 @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
     ARMCPU *cpu = env_archcpu(env);
     uint32_t zcr_len = cpu->sve_max_vq - 1;
 
-    if (el <= 1) {
+    if (el <= 1 &&
+        (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
         zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]);
     }
     if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) {
-- 
2.25.1

[PATCH 2/4] target/arm: Tidy sve_exception_el for CPACR_EL1 access

[Richard Henderson]

Extract entire fields for ZEN and FPEN, rather than testing specific bits.
This makes it easier to follow the code versus the ARM spec.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/helper.c | 36 +++++++++++++++++-------------------
 1 file changed, 17 insertions(+), 19 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index d9ee2ba5f4..cd48560786 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6154,30 +6154,28 @@ int sve_exception_el(CPUARMState *env, int el)
     uint64_t hcr_el2 = arm_hcr_el2_eff(env);
 
     if (el <= 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
-        bool disabled = false;
-
-        /* The CPACR.ZEN controls traps to EL1:
-         * 0, 2 : trap EL0 and EL1 accesses
-         * 1    : trap only EL0 accesses
-         * 3    : trap no accesses
-         */
-        if (!extract32(env->cp15.cpacr_el1, 16, 1)) {
-            disabled = true;
-        } else if (!extract32(env->cp15.cpacr_el1, 17, 1)) {
-            disabled = el == 0;
-        }
-        if (disabled) {
+        /* Check CPACR.ZEN.  */
+        switch (extract32(env->cp15.cpacr_el1, 16, 2)) {
+        case 1:
+            if (el != 0) {
+                break;
+            }
+            /* fall through */
+        case 0:
+        case 2:
             /* route_to_el2 */
             return hcr_el2 & HCR_TGE ? 2 : 1;
         }
 
         /* Check CPACR.FPEN.  */
-        if (!extract32(env->cp15.cpacr_el1, 20, 1)) {
-            disabled = true;
-        } else if (!extract32(env->cp15.cpacr_el1, 21, 1)) {
-            disabled = el == 0;
-        }
-        if (disabled) {
+        switch (extract32(env->cp15.cpacr_el1, 20, 2)) {
+        case 1:
+            if (el != 0) {
+                break;
+            }
+            /* fall through */
+        case 0:
+        case 2:
             return 0;
         }
     }
-- 
2.25.1

[PATCH 3/4] target/arm: Fix {fp, sve}_exception_el for VHE mode running

[Richard Henderson]

When HCR_EL2.E2H is set, the format of CPTR_EL2 changes to
look more like CPACR_EL1, with ZEN and FPEN fields instead
of TZ and TFP fields.

Reported-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/helper.c | 77 +++++++++++++++++++++++++++++++++++----------
 1 file changed, 60 insertions(+), 17 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index cd48560786..ca916139e8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6180,15 +6180,41 @@ int sve_exception_el(CPUARMState *env, int el)
         }
     }
 
-    /* CPTR_EL2.  Since TZ and TFP are positive,
-     * they will be zero when EL2 is not present.
+    /*
+     * CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE).
      */
-    if (el <= 2 && arm_is_el2_enabled(env)) {
-        if (env->cp15.cptr_el[2] & CPTR_TZ) {
-            return 2;
-        }
-        if (env->cp15.cptr_el[2] & CPTR_TFP) {
-            return 0;
+    if (el <= 2) {
+        if (hcr_el2 & HCR_E2H) {
+            /* Check CPTR_EL2.ZEN.  */
+            switch (extract32(env->cp15.cptr_el[2], 16, 2)) {
+            case 1:
+                if (el != 0 || !(hcr_el2 & HCR_TGE)) {
+                    break;
+                }
+                /* fall through */
+            case 0:
+            case 2:
+                return 2;
+            }
+
+            /* Check CPTR_EL2.FPEN.  */
+            switch (extract32(env->cp15.cptr_el[2], 20, 2)) {
+            case 1:
+                if (el == 2 || !(hcr_el2 & HCR_TGE)) {
+                    break;
+                }
+                /* fall through */
+            case 0:
+            case 2:
+                return 0;
+            }
+        } else if (arm_is_el2_enabled(env)) {
+            if (env->cp15.cptr_el[2] & CPTR_TZ) {
+                return 2;
+            }
+            if (env->cp15.cptr_el[2] & CPTR_TFP) {
+                return 0;
+            }
         }
     }
 
@@ -12909,6 +12935,8 @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
 int fp_exception_el(CPUARMState *env, int cur_el)
 {
 #ifndef CONFIG_USER_ONLY
+    uint64_t hcr_el2;
+
     /* CPACR and the CPTR registers don't exist before v6, so FP is
      * always accessible
      */
@@ -12932,13 +12960,15 @@ int fp_exception_el(CPUARMState *env, int cur_el)
         return 0;
     }
 
+    hcr_el2 = arm_hcr_el2_eff(env);
+
     /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
      * 0, 2 : trap EL0 and EL1/PL1 accesses
      * 1    : trap only EL0 accesses
      * 3    : trap no accesses
      * This register is ignored if E2H+TGE are both set.
      */
-    if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
+    if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
         int fpen = extract32(env->cp15.cpacr_el1, 20, 2);
 
         switch (fpen) {
@@ -12979,15 +13009,28 @@ int fp_exception_el(CPUARMState *env, int cur_el)
         }
     }
 
-    /* For the CPTR registers we don't need to guard with an ARM_FEATURE
-     * check because zero bits in the registers mean "don't trap".
+    /*
+     * CPTR_EL2 is present in v7VE or v8, and changes format
+     * with HCR_EL2.E2H (regardless of TGE).
      */
-
-    /* CPTR_EL2 : present in v7VE or v8 */
-    if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1)
-        && arm_is_el2_enabled(env)) {
-        /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
-        return 2;
+    if (cur_el <= 2) {
+        if (hcr_el2 & HCR_E2H) {
+            /* Check CPTR_EL2.FPEN.  */
+            switch (extract32(env->cp15.cptr_el[2], 20, 2)) {
+            case 1:
+                if (cur_el != 0 || !(hcr_el2 & HCR_TGE)) {
+                    break;
+                }
+                /* fall through */
+            case 0:
+            case 2:
+                return 2;
+            }
+        } else if (arm_is_el2_enabled(env)) {
+            if (env->cp15.cptr_el[2] & CPTR_TFP) {
+                return 2;
+            }
+        }
     }
 
     /* CPTR_EL3 : present in v8 */
-- 
2.25.1

[PATCH 4/4] target/arm: Use CPTR_TFP with CPTR_EL3 in fp_exception_el

[Richard Henderson]

Use the named bit rather than a bare extract32.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index ca916139e8..5610879680 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -13034,7 +13034,7 @@ int fp_exception_el(CPUARMState *env, int cur_el)
     }
 
     /* CPTR_EL3 : present in v8 */
-    if (extract32(env->cp15.cptr_el[3], 10, 1)) {
+    if (env->cp15.cptr_el[3] & CPTR_TFP) {
         /* Trap all FP ops to EL3 */
         return 3;
     }
-- 
2.25.1

Re: [PATCH 4/4] target/arm: Use CPTR_TFP with CPTR_EL3 in fp_exception_el

[Peter Maydell]

On Thu, 27 Jan 2022 at 06:34, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Use the named bit rather than a bare extract32.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index ca916139e8..5610879680 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -13034,7 +13034,7 @@ int fp_exception_el(CPUARMState *env, int cur_el)
>      }
>
>      /* CPTR_EL3 : present in v8 */
> -    if (extract32(env->cp15.cptr_el[3], 10, 1)) {
> +    if (env->cp15.cptr_el[3] & CPTR_TFP) {
>          /* Trap all FP ops to EL3 */
>          return 3;
>      }
> --
> 2.25.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

Re: [PATCH 2/4] target/arm: Tidy sve_exception_el for CPACR_EL1 access

[Peter Maydell]

On Thu, 27 Jan 2022 at 06:34, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Extract entire fields for ZEN and FPEN, rather than testing specific bits.
> This makes it easier to follow the code versus the ARM spec.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

Re: [PATCH 1/4] target/arm: Fix sve_zcr_len_for_el for VHE mode running

[Peter Maydell]

On Thu, 27 Jan 2022 at 06:34, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> When HCR_EL2.{E2H,TGE} == '11', ZCR_EL1 is unused.
>
> Reported-by: Zenghui Yu <yuzenghui@huawei.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/helper.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

Re: [PATCH 3/4] target/arm: Fix {fp, sve}_exception_el for VHE mode running

[Peter Maydell]

On Thu, 27 Jan 2022 at 06:34, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> When HCR_EL2.E2H is set, the format of CPTR_EL2 changes to
> look more like CPACR_EL1, with ZEN and FPEN fields instead
> of TZ and TFP fields.
>
> Reported-by: Zenghui Yu <yuzenghui@huawei.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/helper.c | 77 +++++++++++++++++++++++++++++++++++----------
>  1 file changed, 60 insertions(+), 17 deletions(-)
>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

Re: [PATCH 1/4] target/arm: Fix sve_zcr_len_for_el for VHE mode running

[Zenghui Yu via]

On 2022/1/27 14:34, Richard Henderson wrote:
> When HCR_EL2.{E2H,TGE} == '11', ZCR_EL1 is unused.
> 
> Reported-by: Zenghui Yu <yuzenghui@huawei.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>

Re: [PATCH 2/4] target/arm: Tidy sve_exception_el for CPACR_EL1 access

[Zenghui Yu via]

On 2022/1/27 14:34, Richard Henderson wrote:
> Extract entire fields for ZEN and FPEN, rather than testing specific bits.
> This makes it easier to follow the code versus the ARM spec.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>

Re: [PATCH 3/4] target/arm: Fix {fp,sve}_exception_el for VHE mode running

[Zenghui Yu via]

Hi Richard,

On 2022/1/27 14:34, Richard Henderson wrote:
> +    if (el <= 2) {
> +        if (hcr_el2 & HCR_E2H) {
> +            /* Check CPTR_EL2.ZEN.  */
> +            switch (extract32(env->cp15.cptr_el[2], 16, 2)) {
> +            case 1:
> +                if (el != 0 || !(hcr_el2 & HCR_TGE)) {

It looks to me that the code will be easier to follow if we can
put '!(hcr_el2 & HCR_TGE)' before 'el != 0'.

> +                    break;
> +                }
> +                /* fall through */
> +            case 0:
> +            case 2:
> +                return 2;
> +            }

Regardless, thanks for the fix.

Reviewed-and-tested-by: Zenghui Yu <yuzenghui@huawei.com>

Re: [PATCH 4/4] target/arm: Use CPTR_TFP with CPTR_EL3 in fp_exception_el

[Zenghui Yu via]

On 2022/1/27 14:34, Richard Henderson wrote:
> Use the named bit rather than a bare extract32.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>

Re: [PATCH 0/4] target/arm: SVE fixes versus VHE

[Peter Maydell]

On Thu, 27 Jan 2022 at 06:34, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Fix two problems described in
>
> https://lore.kernel.org/qemu-devel/6cdfd5de-2465-adca-73b3-9c66945cf18a@huawei.com/
>
> with some other minor code cleanup.
>


Applied to target-arm.next, thanks.

-- PMM