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Thu, 13 May 2021 12:35:54 -0700 (PDT) MIME-Version: 1.0 References: <20210430202610.1136687-1-richard.henderson@linaro.org> <20210430202610.1136687-83-richard.henderson@linaro.org> In-Reply-To: <20210430202610.1136687-83-richard.henderson@linaro.org> From: Peter Maydell Date: Thu, 13 May 2021 20:35:42 +0100 Message-ID: Subject: Re: [PATCH v6 82/82] target/arm: Enable SVE2 and related extensions To: Richard Henderson Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, 30 Apr 2021 at 22:37, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/cpu.c | 1 + > target/arm/cpu64.c | 13 +++++++++++++ > 2 files changed, 14 insertions(+) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 0dd623e590..30fd5d5ff7 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1464,6 +1464,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) > > u = cpu->isar.id_isar6; > u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); > + u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); > cpu->isar.id_isar6 = u; > > u = cpu->isar.mvfr0; > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index f0a9e968c9..379f90fab8 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -662,6 +662,7 @@ static void aarch64_max_initfn(Object *obj) > t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); > t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); > t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ > + t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); > cpu->isar.id_aa64isar1 = t; > > t = cpu->isar.id_aa64pfr0; > @@ -702,6 +703,17 @@ static void aarch64_max_initfn(Object *obj) > t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ > cpu->isar.id_aa64mmfr2 = t; > > + t = cpu->isar.id_aa64zfr0; > + t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); > + t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */ > + t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); > + t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); > + t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); > + t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); > + t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); > + t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); > + cpu->isar.id_aa64zfr0 = t; > + > /* Replicate the same data to the 32-bit id registers. */ > u = cpu->isar.id_isar5; > u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ > @@ -718,6 +730,7 @@ static void aarch64_max_initfn(Object *obj) > u = FIELD_DP32(u, ID_ISAR6, FHM, 1); > u = FIELD_DP32(u, ID_ISAR6, SB, 1); > u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1); > + u = FIELD_DP32(u, ID_ISAR6, I8MM, 1); > cpu->isar.id_isar6 = u; > > u = cpu->isar.id_pfr0; Do we need to clear any of these in the "user set has_neon and/or has_vfp to false" code in arm_cpu_realizefn() ? thanks -- PMM