From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:49454)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <peter.maydell@linaro.org>) id 1YlL2B-00042S-8n
	for qemu-devel@nongnu.org; Thu, 23 Apr 2015 13:35:32 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <peter.maydell@linaro.org>) id 1YlL27-00050s-2w
	for qemu-devel@nongnu.org; Thu, 23 Apr 2015 13:35:31 -0400
Received: from mail-ig0-f176.google.com ([209.85.213.176]:33157)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <peter.maydell@linaro.org>) id 1YlL26-00050g-Ut
	for qemu-devel@nongnu.org; Thu, 23 Apr 2015 13:35:27 -0400
Received: by igbpi8 with SMTP id pi8so14363237igb.0
	for <qemu-devel@nongnu.org>; Thu, 23 Apr 2015 10:35:26 -0700 (PDT)
MIME-Version: 1.0
In-Reply-To: <675341343a857a3b860a964280f465cbb86eeaad.1427108387.git.peter.crosthwaite@xilinx.com>
References: <cover.1427108387.git.peter.crosthwaite@xilinx.com>
	<675341343a857a3b860a964280f465cbb86eeaad.1427108387.git.peter.crosthwaite@xilinx.com>
From: Peter Maydell <peter.maydell@linaro.org>
Date: Thu, 23 Apr 2015 18:35:05 +0100
Message-ID: <CAFEAcA8GouReo4z32xg5T9Bo=dDr2qp4WbPnkpT+QR9y+1EQQQ@mail.gmail.com>
Content-Type: text/plain; charset=UTF-8
Subject: Re: [Qemu-devel] [PATCH target-arm v4 02/16] target-arm: cpu64:
 Factor out ARM cortex init
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Cc: Edgar Iglesias <edgar.iglesias@xilinx.com>, zach.pfeffer@xilinx.com, Ryota Ozaki <ozaki.ryota@gmail.com>, QEMU Developers <qemu-devel@nongnu.org>, michals@xilinx.com, =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>

On 23 March 2015 at 11:05, Peter Crosthwaite
<peter.crosthwaite@xilinx.com> wrote:
> In preparation for support for Cortex a53. Use "axx" to describe the
> shareable features. Some of the CP15 registers (such as ACTLR) are
> specific to implementation, but we currently just RAZ them so continue
> with that as the policy for all cortex A processors under a shared
> definition.
>
> The cache sizes and geometeries, the L1 I-cache policy and the physical
> address range differ between A53 and A57 so those particulars are left
> as A57 specific. The rest are moved to the generalisation.

I'm not a huge fan of this as it seems unlikely that every CPU
with a "Cortex-Axx" is going to look so similar to the A57.

Call the reginfo table cortex_a53_a57_cp_reginfo if you want
to share it, but I would leave the initfns completely separate
personally.

-- PMM