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From: Peter Maydell <peter.maydell@linaro.org>
To: "Alex Bennée" <alex.bennee@linaro.org>
Cc: qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v3 2/5] target/arm: relax permission checks for HWCAP_CPUID registers
Date: Thu, 28 Jun 2018 15:25:01 +0100	[thread overview]
Message-ID: <CAFEAcA8JHHp2oVvUqX0oGhc+R7u1PNCWW1Q052ujpTx9WbVNDw@mail.gmail.com> (raw)
In-Reply-To: <20180625160009.17437-3-alex.bennee@linaro.org>

On 25 June 2018 at 17:00, Alex Bennée <alex.bennee@linaro.org> wrote:
> Although technically not visible to userspace the kernel does make
> them visible via trap and emulate. For user mode we can provide the
> value directly but we need to relax our permission checks to do this.
>
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> ---
>  target/arm/helper.c | 14 +++++++++++++-
>  1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 6e6b1762e8..9d81feb124 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -5813,7 +5813,19 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
>      if (r->state != ARM_CP_STATE_AA32) {
>          int mask = 0;
>          switch (r->opc1) {
> -        case 0: case 1: case 2:
> +        case 0:
> +#ifdef CONFIG_USER_ONLY
> +            /* Some AArch64 CPU ID/feature are exported to userspace
> +             * by the kernel (see HWCAP_CPUID) */
> +            if (r->opc0 == 3 && r->crn == 0 &&
> +                (r->crm == 0 ||
> +                 (r->crm >= 4 && r->crm <= 7))) {
> +                mask = PL0_R;
> +                break;
> +            }
> +#endif
> +            /* fall-through */
> +        case 1: case 2:
>              /* min_EL EL1 */
>              mask = PL1_RW;
>              break;

This looks like a rather inelegant place to shove a CONFIG_USER_ONLY
special case. Isn't there a cleaner way to do whatever this is trying
to achieve?

thanks
-- PMM

  parent reply	other threads:[~2018-06-28 14:25 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-25 16:00 [Qemu-devel] [PATCH v3 0/5] support reading some CPUID/CNT registers from user-space Alex Bennée
2018-06-25 16:00 ` [Qemu-devel] [PATCH v3 1/5] target/arm: support reading of CNT[VCT|FRQ]_EL0 " Alex Bennée
2018-06-27  4:52   ` Richard Henderson
2018-06-27 16:57   ` Emilio G. Cota
2018-06-25 16:00 ` [Qemu-devel] [PATCH v3 2/5] target/arm: relax permission checks for HWCAP_CPUID registers Alex Bennée
2018-06-27  5:25   ` Richard Henderson
2018-06-28 14:25   ` Peter Maydell [this message]
2018-06-28 14:39     ` Alex Bennée
2018-06-25 16:00 ` [Qemu-devel] [PATCH v3 3/5] target/arm: expose CPUID registers to userspace Alex Bennée
2018-06-28 14:23   ` Peter Maydell
2018-06-25 16:00 ` [Qemu-devel] [PATCH v3 4/5] linux-user/elfload: enable HWCAP_CPUID for AArch64 Alex Bennée
2018-06-27  5:27   ` Richard Henderson
2018-06-25 16:00 ` [Qemu-devel] [PATCH v3 5/5] tests/tcg/aarch64: userspace system register test Alex Bennée
2018-06-25 20:51   ` Alex Bennée
2018-06-27  5:38   ` Richard Henderson
2018-06-28 15:06 ` [Qemu-devel] [PATCH v3 0/5] support reading some CPUID/CNT registers from user-space Peter Maydell

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