From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3152C43334 for ; Tue, 5 Jul 2022 14:14:08 +0000 (UTC) Received: from localhost ([::1]:37216 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o8jJY-00030C-1t for qemu-devel@archiver.kernel.org; Tue, 05 Jul 2022 10:14:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56176) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o8jI5-00012k-U3 for qemu-devel@nongnu.org; Tue, 05 Jul 2022 10:12:37 -0400 Received: from mail-yw1-x112b.google.com ([2607:f8b0:4864:20::112b]:45025) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o8jHv-0001il-0h for qemu-devel@nongnu.org; Tue, 05 Jul 2022 10:12:37 -0400 Received: by mail-yw1-x112b.google.com with SMTP id 00721157ae682-31cb2c649f7so35714827b3.11 for ; Tue, 05 Jul 2022 07:12:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=UqsobVuHM5F53h11JRDooFYJPVur6KDy5QXdIciqs7I=; b=yxv6JOV9rlORgTfxHCQc745Aw2SDyLvgy0ZwEpQRO20/j9Ojxb3NGWJe91/GC3YleN yO1Bils3vch93oxVVqCIkikPObLBlhsbFR/rHwY2JI6PoQZRV/kUUr1hDBcFctLO5My1 +x+cIEd0XQfP8ldTfAuJ9KPR7dMlw4BqmQezHIJJB6F0YF6NJKt4KrXmbLzQPLKR7hHl MYYBghi/ioD7T1YVPYCzs2dKqRHNEtSE5lKkDFUx9jZHh0k3dO+cYKWLdCGfXf4t4Ejv 7IeWh4YE0uIF5dOTn94Nr3ytAmpznUHIHZv2YqA9meol9uIrBRoVllfbQRDzcbDpPrUa QIeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=UqsobVuHM5F53h11JRDooFYJPVur6KDy5QXdIciqs7I=; b=goq34gf4f2CGeWbRj2gEGsqOJwoAOErh8lUa4AYzONgmkh0Ds3cSVYLehL5S4uqRX8 oW4kTSVU3LL+4rrvqY3mnDp8VXrs8yVfgKtljx70JJCFsoYk3/dSCWfBU2YTlljOc7+M bTAo5TvHYd9a7sega2uJYuEpXnitV9dUHMvOkbfb/FYqLw6LRpUpt5SQftct3iUxPvZa dmhs/v2+eF714yDG+pnO4J6OFbuPMsaZ/60IoXOy5jXCXfN2Vzgf9XMUFA+xypXgQFwe F8UM7NRL/0BjizJlUduMOrG9i2QnTk0OdLvG12lfIyMrFJOWphBSKEF3Riacj80yGWIz zV7Q== X-Gm-Message-State: AJIora812SUnmfVOnj8qsTT6mcTObT76gYW8HCv3t9XKjRmE0iA2ba+5 Rx98sqOLz/s433mj2svdwTdhLjHX73Rf6J8okNmSLg== X-Google-Smtp-Source: AGRyM1uBqEifq6cf04yFPg/iodR/OTcexcWStB7O/TtZFII8DQeWLL5wu7/82yn6I+XV64TlGe038yKz4MGaees9bZ8= X-Received: by 2002:a81:6a85:0:b0:31c:8624:b065 with SMTP id f127-20020a816a85000000b0031c8624b065mr17948485ywc.64.1657030345691; Tue, 05 Jul 2022 07:12:25 -0700 (PDT) MIME-Version: 1.0 References: <20220703082419.770989-1-richard.henderson@linaro.org> <20220703082419.770989-7-richard.henderson@linaro.org> In-Reply-To: <20220703082419.770989-7-richard.henderson@linaro.org> From: Peter Maydell Date: Tue, 5 Jul 2022 15:12:14 +0100 Message-ID: Subject: Re: [PATCH 06/62] target/arm: Use PageEntryExtra for BTI To: Richard Henderson Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::112b; envelope-from=peter.maydell@linaro.org; helo=mail-yw1-x112b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Sun, 3 Jul 2022 at 09:27, Richard Henderson wrote: > > Add a bit to ARMCacheAttrs to hold the guarded bit between > get_phys_addr_lpae and arm_cpu_tlb_fill, then put the bit > into PageEntryExtra. > > In is_guarded_page, use probe_access_extra instead of just > guessing that the tlb entry is still present. Also handles > the FIXME about executing from device memory. > > Signed-off-by: Richard Henderson > --- Reviewed-by: Peter Maydell thanks -- PMM