From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43493) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1agFTE-0007RT-Tu for qemu-devel@nongnu.org; Wed, 16 Mar 2016 13:42:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1agFTD-0000iX-TB for qemu-devel@nongnu.org; Wed, 16 Mar 2016 13:42:56 -0400 Received: from mail-vk0-x22e.google.com ([2607:f8b0:400c:c05::22e]:36064) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1agFTD-0000iP-Fh for qemu-devel@nongnu.org; Wed, 16 Mar 2016 13:42:55 -0400 Received: by mail-vk0-x22e.google.com with SMTP id c3so71311449vkb.3 for ; Wed, 16 Mar 2016 10:42:55 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1458148715-16864-1-git-send-email-peter.maydell@linaro.org> References: <1458148715-16864-1-git-send-email-peter.maydell@linaro.org> From: Peter Maydell Date: Wed, 16 Mar 2016 17:42:35 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PULL 00/21] target-arm queue List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: QEMU Developers On 16 March 2016 at 17:18, Peter Maydell wrote: > Here's the target-arm queue; I'm a bit hesitant about the late-landing > various new board/SoC patches, but they won't affect anybody who isn't > trying to use those boards, so I think it's OK. > > (There are a few other patches on list which I definitely want to > get in before rc0 but they need a bit more review time I think.) > > thanks > -- PMM > > > The following changes since commit 0ebc03bc065329eaefb6493f5fa7df08df528f= 2a: > > util/base64.c: Clean includes (2016-03-16 12:48:11 +0000) > > are available in the git repository at: > > git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-= 20160316 > > for you to fetch changes up to 10b27d1ab391dbf36f92e1a33179662082401d7a: > > sd: Fix "info qtree" on boards with SD cards (2016-03-16 17:12:46 +0000= ) > > ---------------------------------------------------------------- > target-arm queue: > * loader: Fix incorrect parameter name in load_image_mr() > * Implement MRS (banked) and MSR (banked) instructions > * virt: Implement versioning for machine model > * i.MX: some initial patches preparing for i.MX6 support > * new ASPEED AST2400 SoC and palmetto-bmc machine > * bcm2835: add some more raspi2 devices > * sd: fix segfault running "info qtree" Some versions of gcc appear to give false positive 'may be used uninitialized' warnings about the msr/mrs code: /home/petmay01/linaro/qemu-for-merges/target-arm/translate.c: In function =E2=80=98gen_msr_banked .isra.45=E2=80=99: /home/petmay01/linaro/qemu-for-merges/target-arm/translate.c:4321:17: error: =E2=80=98tgtmode=E2=80=99 ma y be used uninitialized in this function [-Werror=3Dmaybe-uninitialized] tcg_tgtmode =3D tcg_const_i32(tgtmode); ^ /home/petmay01/linaro/qemu-for-merges/target-arm/translate.c:4322:15: error: =E2=80=98regno=E2=80=99 may be used uninitialized in this function [-Werror=3Dmaybe-uninitialized] tcg_regno =3D tcg_const_i32(regno); ^ /home/petmay01/linaro/qemu-for-merges/target-arm/translate.c: In function =E2=80=98gen_mrs_banked.isra.48=E2=80=99: /home/petmay01/linaro/qemu-for-merges/target-arm/translate.c:4343:17: error: =E2=80=98tgtmode=E2=80=99 may be used uninitialized in this function [-Werror=3Dmaybe-uninitialized] tcg_tgtmode =3D tcg_const_i32(tgtmode); ^ /home/petmay01/linaro/qemu-for-merges/target-arm/translate.c:4344:15: error: =E2=80=98regno=E2=80=99 may be used uninitialized in this function [-Werror=3Dmaybe-uninitialized] tcg_regno =3D tcg_const_i32(regno); ^ Fixup: --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -4308,7 +4308,7 @@ undef: static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn) { TCGv_i32 tcg_reg, tcg_tgtmode, tcg_regno; - int tgtmode, regno; + int tgtmode =3D 0, regno =3D 0; if (!msr_banked_access_decode(s, r, sysm, rn, &tgtmode, ®no)) { return; @@ -4330,7 +4330,7 @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn) static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn) { TCGv_i32 tcg_reg, tcg_tgtmode, tcg_regno; - int tgtmode, regno; + int tgtmode =3D 0, regno =3D 0; if (!msr_banked_access_decode(s, r, sysm, rn, &tgtmode, ®no)) { return; which I'll squash into the appropriate patch and respin. thanks -- PMM