From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CBFDC433EF for ; Mon, 6 Sep 2021 09:27:33 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2091F60F70 for ; Mon, 6 Sep 2021 09:27:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 2091F60F70 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:49706 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mNAua-0008D5-AV for qemu-devel@archiver.kernel.org; Mon, 06 Sep 2021 05:27:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33740) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mNAsu-0006rY-Vi for qemu-devel@nongnu.org; Mon, 06 Sep 2021 05:25:49 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:37683) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mNAst-0006yS-5x for qemu-devel@nongnu.org; Mon, 06 Sep 2021 05:25:48 -0400 Received: by mail-wr1-x433.google.com with SMTP id v10so8824995wrd.4 for ; Mon, 06 Sep 2021 02:25:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=THfGlBol6wmZdZN87ntqx1yN+eYUhN7rrliCHA5eOr4=; b=axZ4jE7f28P0dF8FcAEkcWfS/FlLq3kYWlAYbAmYZvcNHZnQrboonegJ2ogpYo0EoZ wXnfYcFN1IUQSCB3qYk9Qq66yXBwppBqZTvRFnfAGATEnE5e/qc626F8Uye21OqwKZrk t7QyGkmrfQfrLUyCmW3lnTZw2ieXl38gAENK09hiopNwAhklSGQ2O7no3el5FAvYNlN0 uH4QGvilMu6nvwC2QZJ2PPyyZNKadGjBn/9PXuZOjzB2LVDqZ2KPlmWhIJv3gYKgEWFP W/OhjUftj9No3UuaPiUZ3D/FVr2jNND0WraNH586q8GQg52VYSkwtookY8fr425H93tN 61Cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=THfGlBol6wmZdZN87ntqx1yN+eYUhN7rrliCHA5eOr4=; b=LkjpBbiKqsPkhd5aW9rTaBMhzWVZzGxhk3fu4WJDe7AwpFS1xZz6Dy4lTIlji/3FfU ns5mN5HPGQzCKmVqsmuThgOE66ffTshKsRXi0BwGWafJa0Hmg28Tz5rXHCNsMr1DnwzH D7s/Vsj+Ju+wlPCtKRTvm34fyfnZpX1ce4UMlUBrnNYmdqAPIFby7p4IAO+WMtpvdgc/ qlNZn4GQRDAuIyqMYLxtRLAUcLsI4Y9Yv2KD4bWUKPcylS5Q3AaqNdo/RZd0k0HRbSEw MofD5DjYksCCtlLfBJXPLTAq9LSEhMovQKrnnm1y9sojKehISbqGoQONbiCgc98pLfgH xHkg== X-Gm-Message-State: AOAM532cwtXDBc8feI92eunQB5xnSNbyjcMK6mmNeBnWEM4j2H/cxPyY 2fAO72jTPmkZCchSIWKDXlkW/ww7t80a0iQxzEXonR/kkDw+HA== X-Google-Smtp-Source: ABdhPJxLo66IKaBsI9rw3n0/b96iQmzVNf67KjKffBBjKb/mJOEb+PqbrPcTgpfElJYUCBhqLCX6Pc1612HybqhOW9A= X-Received: by 2002:a5d:4647:: with SMTP id j7mr12316867wrs.149.1630920345019; Mon, 06 Sep 2021 02:25:45 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Peter Maydell Date: Mon, 6 Sep 2021 10:24:55 +0100 Message-ID: Subject: =?UTF-8?Q?Re=3A_How_does_qemu_detect_the_completion_of_interrupt?= =?UTF-8?Q?_execution=EF=BC=9F?= To: Duo jia Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, 6 Sept 2021 at 03:47, Duo jia wrote: > > Thank you for your explanation. > >> And finishing the execution of the interrupt routine will automatically >> allow a pending second interrupt to be taken immediately > > > I think this is a hardware feature. But how to achieve it with qemu That is what my explanation was trying to tell you how to do. In a bit more detail: * your interrupt controller device should assert the irq line to the CPU for as long as there is any pending interrupt (regardless of its priority). It should deassert it when there is no longer a pending interrupt (ie when the guest writes to the interrupt status register to clear the pending status of an interrupt, if that was the only pending interrupt then the interrupt controller should stop asserting the irq line). * your stm8_cpu_set_irq function should set and clear the CPU_INTERRUPT_HARD flag in interrupt_request so that it follows the irq line value * your .cpu_exec_interrupt function should only take the interrupt if the CCR.I1/I0 bits permit it. Otherwise it should return false (telling the QEMU core code that there was no interrupt taken). cpu_exec_interrupt should *not* clear the CPU_INTERRUPT_HARD flag, whether it decides to take an interrupt or not. * your do_interrupt function should set CCR.I1/I0 from the ITC_SPRx registers (as well as doing everything else that interrupt entry needs to do) * your implementation of iret should reload the CCR.I1/I0 bits, the way the spec describes There are other ways to structure this (mostly involving tying the interrupt controller model and the CPU model together more closely), but the above is the "classic" and probably simplest way of doing it. -- PMM