From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46661) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecBEJ-0007OA-Q8 for qemu-devel@nongnu.org; Thu, 18 Jan 2018 09:31:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ecBEJ-0006zW-1p for qemu-devel@nongnu.org; Thu, 18 Jan 2018 09:31:47 -0500 Received: from mail-ot0-x22f.google.com ([2607:f8b0:4003:c0f::22f]:36692) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ecBEI-0006yk-Rg for qemu-devel@nongnu.org; Thu, 18 Jan 2018 09:31:46 -0500 Received: by mail-ot0-x22f.google.com with SMTP id f100so7654338otf.3 for ; Thu, 18 Jan 2018 06:31:46 -0800 (PST) MIME-Version: 1.0 In-Reply-To: References: <20180109122252.17670-1-alex.bennee@linaro.org> <20180109122252.17670-11-alex.bennee@linaro.org> <1393deaf-c207-6055-1f7c-f7ae814cf2db@amsat.org> <87shb3nwkc.fsf@linaro.org> From: Peter Maydell Date: Thu, 18 Jan 2018 14:31:25 +0000 Message-ID: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v2 10/20] fpu/softfloat: define decompose structures List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: =?UTF-8?B?QWxleCBCZW5uw6ll?= , Francisco Iglesias , Richard Henderson , Laurent Vivier , QEMU Developers , Andrew Dutcher , bharata@linux.vnet.ibm.com, Aurelien Jarno On 18 January 2018 at 14:26, Philippe Mathieu-Daud=C3=A9 = wrote: > > > Le 18 janv. 2018 10:09 AM, "Alex Benn=C3=A9e" a = =C3=A9crit : > > > Philippe Mathieu-Daud=C3=A9 writes: >>> +typedef struct { >>> + uint64_t frac : 64; >> >> I think this does not work on LLP64/IL32P64 model. >> >> Should we add a check in ./configure and refuse to build on IL32P64 >> model? This would be safer IMHO. >> >>> + int exp : 32; >>> + float_class cls : 8; >>> + int : 23; >>> + bool sign : 1; >> >> checking on "ISO/IEC 14882:1998" 9.6 Bit-fields: >> >> Alignment of bit-fields is implementation-defined. Bit-fields are packed >> into some addressable allocation unit. [Note: bit-fields straddle >> allocation units on some machines and not on others. Bit-fields are >> assigned right-to-left on some machines, left-to-right on others. ] >> >> I'd still write it: >> >> int :23, sign :1; >> >>> +} decomposed_parts; > > I think rather than stuff it into bit fields we can just leave it up to > the compiler? > > > Yep, my only worry here is the IL32P64 model, if we care. I don't think we care much about IL32P64, but the code should still work there, right? It doesn't actually make any assumptions about bitfield layout. I think I agree that we shouldn't use bitfields here if we don't need to, though. thanks -- PMM