[RISU PATCH 0/2] arm.risu: two minor fixes

[RISU PATCH 0/2] arm.risu: two minor fixes

[Peter Maydell]

These are a couple of minor fixes to arm.risu patterns.
(They're a prereq at least textually to the fp16 arm.risu
change, and I should have sent them out with that but I forgot
I had them in my patchstack.)

thanks
-- PMM

Peter Maydell (2):
  arm.risu: Correct VLDR/VSTR U=0 patterns
  arm.risu: Fix typo in VCVT_B_TT pattern name

 arm.risu | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

-- 
2.20.1

[PATCH 1/2] arm.risu: Correct VLDR/VSTR U=0 patterns

[Peter Maydell]

Correct the VLDR and VSTR patterns, which claimed to be setting U=0
but in fact left it identical to the U=1 pattern due to a
cut-and-paste error.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
Somehow the pre-generated test binaries I have from Alex have
U=0 insns in them -- I suspect this got fixed locally but never
made it upstream ?
---
 arm.risu | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arm.risu b/arm.risu
index f8b6deb..43a72ae 100644
--- a/arm.risu
+++ b/arm.risu
@@ -757,7 +757,7 @@ VLDM A1c cond:4 110 p u d 1 1 rn:4 vd:4 101 x imm:8 !constraints { $p == $u; }
 VSTR A1a cond:4 1101 1 d 00 rn:4 vd:4 101 x imm:8 \
  !memory { reg_plus_imm($rn, $imm * 4); }
 # both A1 and A2 encodings, U = 0
-VSTR A1b cond:4 1101 1 d 00 rn:4 vd:4 101 x imm:8 \
+VSTR A1b cond:4 1101 0 d 00 rn:4 vd:4 101 x imm:8 \
  !memory { reg_minus_imm($rn, $imm * 4); }
 
 # VLDR
@@ -765,7 +765,7 @@ VSTR A1b cond:4 1101 1 d 00 rn:4 vd:4 101 x imm:8 \
 VLDR A1a cond:4 1101 1 d 01 rn:4 vd:4 101 x imm:8 \
  !memory { reg_plus_imm($rn, $imm * 4); }
 # both A1 and A2 encodings, U = 0
-VLDR A1b cond:4 1101 1 d 01 rn:4 vd:4 101 x imm:8 \
+VLDR A1b cond:4 1101 0 d 01 rn:4 vd:4 101 x imm:8 \
  !memory { reg_minus_imm($rn, $imm * 4); }
 
 ########### Extension register transfer ###################
-- 
2.20.1

[PATCH 2/2] arm.risu: Fix typo in VCVT_B_TT pattern name

[Peter Maydell]

Fix typo in VCVT_B_TT pattern name.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 arm.risu | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arm.risu b/arm.risu
index 43a72ae..048215b 100644
--- a/arm.risu
+++ b/arm.risu
@@ -669,7 +669,7 @@ VABS A2 cond:4 11101 d 11 0000 vd:4 101 sz 1 1 m 0 vm:4
 VNEG A2 cond:4 11101 d 11 0001 vd:4 101 sz 0 1 m 0 vm:4
 VSQRT A1 cond:4 11101 d 11 0001 vd:4 101 sz 1 1 m 0 vm:4
 # VCVTB, VCVTT (A8.6.300) [requires half-precision extension]
-VCTV_B_TT A1 cond:4 1110 1 d 11 001 op vd:4 101 0 t 1 m 0 vm:4
+VCVT_B_TT A1 cond:4 1110 1 d 11 001 op vd:4 101 0 t 1 m 0 vm:4
 VCMP A1 cond:4 11101 d 11 0100 vd:4 101 sz e 1 m 0 vm:4
 VCMP A2 cond:4 11101 d 11 0101 vd:4 101 sz e 1 0 0 0000
 
-- 
2.20.1

Re: [RISU PATCH 0/2] arm.risu: two minor fixes

[Peter Maydell]

Ping for review? Mostly I'm interested in whether either
Richard or Alex knows what's up with the discrepancy between
the VLDR/VSTR patterns in current risu and the generated
aarch32 binaries/traces that have been floating around...

thanks
-- PMM

On Tue, 1 Sep 2020 at 17:20, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> These are a couple of minor fixes to arm.risu patterns.
> (They're a prereq at least textually to the fp16 arm.risu
> change, and I should have sent them out with that but I forgot
> I had them in my patchstack.)
>
> thanks
> -- PMM
>
> Peter Maydell (2):
>   arm.risu: Correct VLDR/VSTR U=0 patterns
>   arm.risu: Fix typo in VCVT_B_TT pattern name
>
>  arm.risu | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

Re: [PATCH 1/2] arm.risu: Correct VLDR/VSTR U=0 patterns

[Alex Bennée]

Peter Maydell <peter.maydell@linaro.org> writes:

> Correct the VLDR and VSTR patterns, which claimed to be setting U=0
> but in fact left it identical to the U=1 pattern due to a
> cut-and-paste error.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> Somehow the pre-generated test binaries I have from Alex have
> U=0 insns in them -- I suspect this got fixed locally but never
> made it upstream ?

Hmm my current set of aarch32 test patterns have U=1 throughout. So if
it did get fixed locally it also got lost.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

-- 
Alex Bennée

Re: [PATCH 2/2] arm.risu: Fix typo in VCVT_B_TT pattern name

[Alex Bennée]

Peter Maydell <peter.maydell@linaro.org> writes:

> Fix typo in VCVT_B_TT pattern name.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

-- 
Alex Bennée

Re: [PATCH 1/2] arm.risu: Correct VLDR/VSTR U=0 patterns

[Peter Maydell]

On Mon, 14 Sep 2020 at 14:42, Alex Bennée <alex.bennee@linaro.org> wrote:
>
>
> Peter Maydell <peter.maydell@linaro.org> writes:
>
> > Correct the VLDR and VSTR patterns, which claimed to be setting U=0
> > but in fact left it identical to the U=1 pattern due to a
> > cut-and-paste error.
> >
> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> > ---
> > Somehow the pre-generated test binaries I have from Alex have
> > U=0 insns in them -- I suspect this got fixed locally but never
> > made it upstream ?
>
> Hmm my current set of aarch32 test patterns have U=1 throughout. So if
> it did get fixed locally it also got lost.

I'm surprised you don't see test failures due to the memory
constraint not matching up with the encoding...

-- PMM