From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:60559) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RuosR-000623-1M for qemu-devel@nongnu.org; Tue, 07 Feb 2012 12:30:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RuosM-0004aH-Qt for qemu-devel@nongnu.org; Tue, 07 Feb 2012 12:30:47 -0500 Received: from mail-qw0-f52.google.com ([209.85.216.52]:50556) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RuosM-0004aB-Jd for qemu-devel@nongnu.org; Tue, 07 Feb 2012 12:30:42 -0500 Received: by qafi31 with SMTP id i31so4441878qaf.4 for ; Tue, 07 Feb 2012 09:30:42 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <1328237992-14953-8-git-send-email-afaerber@suse.de> References: <1328237992-14953-1-git-send-email-afaerber@suse.de> <1328237992-14953-8-git-send-email-afaerber@suse.de> Date: Tue, 7 Feb 2012 17:30:42 +0000 Message-ID: From: Peter Maydell Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH RFC v3 07/21] target-arm: Overwrite reset handler for ti925t List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?Q?Andreas_F=C3=A4rber?= Cc: qemu-devel@nongnu.org On 3 February 2012 02:59, Andreas F=C3=A4rber wrote: > The OMAPCP feature allows to switch between TI915T and TI925T via > cp15 c15_ticonfig register. Move reset into ti925t-specific callback. > > Signed-off-by: Andreas F=C3=A4rber > Cc: Peter Maydell > --- > =C2=A0target-arm/cpu.c =C2=A0 =C2=A0| =C2=A0 18 ++++++++++++++++++ > =C2=A0target-arm/helper.c | =C2=A0 =C2=A01 - > =C2=A02 files changed, 18 insertions(+), 1 deletions(-) > > diff --git a/target-arm/cpu.c b/target-arm/cpu.c > index b794ec1..a6dbad3 100644 > --- a/target-arm/cpu.c > +++ b/target-arm/cpu.c > @@ -99,6 +99,23 @@ typedef struct ARMCPUInfo { > =C2=A0 =C2=A0 void (*class_init)(ARMCPUClass *klass, const struct ARMCPUI= nfo *info); > =C2=A0} ARMCPUInfo; > > +static void ti925t_reset(CPU *c) > +{ > + =C2=A0 =C2=A0ARMCPU *cpu =3D ARM_CPU(c); > + =C2=A0 =C2=A0CPUARMState *env =3D &cpu->env; > + > + =C2=A0 =C2=A0arm_cpu_reset(c); > + > + =C2=A0 =C2=A0env->cp15.c0_cpuid =3D ARM_CPUID_TI925T; /* Depends on wir= ing. */ > +} If/when I finish my cp15 cleanup series this will become unnecessary, becau= se c0_cpuid will just be another cp15 register among many which the CPU define= s in its init function somewhere (and the cp15 register struct will include "reset value for this cp15 register" and arm_cpu_reset() will just enumerat= e them all and set them to their reset values). -- PMM