* [Qemu-devel] [PULL 00/10] target-arm queue
@ 2015-03-11 14:18 Peter Maydell
2015-03-11 14:18 ` [Qemu-devel] [PULL 01/10] hw/arm/virt: fix cmdline parsing bug with CPU options and smp > 1 Peter Maydell
` (10 more replies)
0 siblings, 11 replies; 32+ messages in thread
From: Peter Maydell @ 2015-03-11 14:18 UTC (permalink / raw)
To: qemu-devel
target-arm queue: mostly bug fixes, but also the Netduino 2
machine model. I'm letting that in (even though it's nearly
hardfreeze) since a new board model isn't going to impact
other existing uses, and the patches were posted well before
softfreeze deadline.
-- PMM
The following changes since commit 48412371415a260d00fc7fdcdb400da55f268828:
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging (2015-03-11 11:12:35 +0000)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150311
for you to fetch changes up to 4f9950520a115acf9c0a209f0befa45758ad0215:
bitops.h: sextract64() return type should be int64_t, not uint64_t (2015-03-11 13:21:06 +0000)
----------------------------------------------------------------
target-arm queue:
* fix a bug in bitops.h
* implement SD card support on integratorcp
* add a missing 'compatible' property for Cortex-A57
* add Netduino 2 machine model
* fix command line parsing bug for CPU options with multiple CPUs
----------------------------------------------------------------
Alistair Francis (5):
stm32f2xx_timer: Add the stm32f2xx Timer
stm32f2xx_USART: Add the stm32f2xx USART Controller
stm32f2xx_SYSCFG: Add the stm32f2xx SYSCFG
stm32f205: Add the stm32f205 SoC
netduino2: Add the Netduino 2 Machine
Ard Biesheuvel (1):
hw/arm/virt: fix cmdline parsing bug with CPU options and smp > 1
Jan Kiszka (2):
integrator/cp: Model CP control registers as sysbus device
integrator/cp: Implement CARDIN and WPROT signals
Peter Maydell (1):
bitops.h: sextract64() return type should be int64_t, not uint64_t
Ryota Ozaki (1):
target-arm: Add missing compatible property to A57
default-configs/arm-softmmu.mak | 4 +
hw/arm/Makefile.objs | 2 +
hw/arm/integratorcp.c | 95 +++++++++--
hw/arm/netduino2.c | 57 +++++++
hw/arm/stm32f205_soc.c | 160 ++++++++++++++++++
hw/arm/virt.c | 4 +-
hw/char/Makefile.objs | 1 +
hw/char/stm32f2xx_usart.c | 229 ++++++++++++++++++++++++++
hw/misc/Makefile.objs | 1 +
hw/misc/stm32f2xx_syscfg.c | 160 ++++++++++++++++++
hw/timer/Makefile.objs | 2 +
hw/timer/stm32f2xx_timer.c | 328 +++++++++++++++++++++++++++++++++++++
include/hw/arm/stm32f205_soc.h | 57 +++++++
include/hw/char/stm32f2xx_usart.h | 73 +++++++++
include/hw/misc/stm32f2xx_syscfg.h | 61 +++++++
include/hw/timer/stm32f2xx_timer.h | 101 ++++++++++++
include/qemu/bitops.h | 2 +-
target-arm/cpu64.c | 1 +
18 files changed, 1323 insertions(+), 15 deletions(-)
create mode 100644 hw/arm/netduino2.c
create mode 100644 hw/arm/stm32f205_soc.c
create mode 100644 hw/char/stm32f2xx_usart.c
create mode 100644 hw/misc/stm32f2xx_syscfg.c
create mode 100644 hw/timer/stm32f2xx_timer.c
create mode 100644 include/hw/arm/stm32f205_soc.h
create mode 100644 include/hw/char/stm32f2xx_usart.h
create mode 100644 include/hw/misc/stm32f2xx_syscfg.h
create mode 100644 include/hw/timer/stm32f2xx_timer.h
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Qemu-devel] [PULL 01/10] hw/arm/virt: fix cmdline parsing bug with CPU options and smp > 1
2015-03-11 14:18 [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell
@ 2015-03-11 14:18 ` Peter Maydell
2015-03-11 14:18 ` [Qemu-devel] [PULL 02/10] stm32f2xx_timer: Add the stm32f2xx Timer Peter Maydell
` (9 subsequent siblings)
10 siblings, 0 replies; 32+ messages in thread
From: Peter Maydell @ 2015-03-11 14:18 UTC (permalink / raw)
To: qemu-devel
From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
The recently introduced feature that allows 32 bit guests to be
executed under KVM on a 64-bit host incorrectly handles the case
where more than 1 cpu is specified using '-smp N'
For instance, this invocation of qemu
qemu-system-aarch64 -M virt -cpu cortex-a57,aarch64=off -smp 2
produces the following error
qemu-system-aarch64: Expected key=value format, found aarch64
which is caused by the destructive parsing performed by
cpu_common_parse_features(), resulting in subsequent attempts
to parse the CPU option string (for each additional CPU) to fail.
So duplicate the string before parsing it, and free it directly
afterwards.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Greg Bellows <greg.bellows@linaro.org>
Message-id: 1425402380-10488-1-git-send-email-ard.biesheuvel@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 93b7605..9072bc2 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -758,6 +758,7 @@ static void machvirt_init(MachineState *machine)
CPUClass *cc = CPU_CLASS(oc);
Object *cpuobj;
Error *err = NULL;
+ char *cpuopts = g_strdup(cpustr[1]);
if (!oc) {
fprintf(stderr, "Unable to find CPU definition\n");
@@ -766,7 +767,8 @@ static void machvirt_init(MachineState *machine)
cpuobj = object_new(object_class_get_name(oc));
/* Handle any CPU options specified by the user */
- cc->parse_features(CPU(cpuobj), cpustr[1], &err);
+ cc->parse_features(CPU(cpuobj), cpuopts, &err);
+ g_free(cpuopts);
if (err) {
error_report("%s", error_get_pretty(err));
exit(1);
--
1.9.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PULL 02/10] stm32f2xx_timer: Add the stm32f2xx Timer
2015-03-11 14:18 [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell
2015-03-11 14:18 ` [Qemu-devel] [PULL 01/10] hw/arm/virt: fix cmdline parsing bug with CPU options and smp > 1 Peter Maydell
@ 2015-03-11 14:18 ` Peter Maydell
2015-03-11 14:18 ` [Qemu-devel] [PULL 03/10] stm32f2xx_USART: Add the stm32f2xx USART Controller Peter Maydell
` (8 subsequent siblings)
10 siblings, 0 replies; 32+ messages in thread
From: Peter Maydell @ 2015-03-11 14:18 UTC (permalink / raw)
To: qemu-devel
From: Alistair Francis <alistair23@gmail.com>
This patch adds the stm32f2xx timers: TIM2, TIM3, TIM4 and TIM5
to QEMU.
Signed-off-by: Alistair Francis <alistair@alistair23.me>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 155091a323390f8da3cca496e4c611c493e62a77.1424175342.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
default-configs/arm-softmmu.mak | 1 +
hw/timer/Makefile.objs | 2 +
hw/timer/stm32f2xx_timer.c | 328 +++++++++++++++++++++++++++++++++++++
include/hw/timer/stm32f2xx_timer.h | 101 ++++++++++++
4 files changed, 432 insertions(+)
create mode 100644 hw/timer/stm32f2xx_timer.c
create mode 100644 include/hw/timer/stm32f2xx_timer.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 149ae1b..bdb6eeb 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -80,6 +80,7 @@ CONFIG_NSERIES=y
CONFIG_REALVIEW=y
CONFIG_ZAURUS=y
CONFIG_ZYNQ=y
+CONFIG_STM32F2XX_TIMER=y
CONFIG_VERSATILE_PCI=y
CONFIG_VERSATILE_I2C=y
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index 2c86c3d..133bd0d 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -31,3 +31,5 @@ obj-$(CONFIG_DIGIC) += digic-timer.o
obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
obj-$(CONFIG_ALLWINNER_A10_PIT) += allwinner-a10-pit.o
+
+common-obj-$(CONFIG_STM32F2XX_TIMER) += stm32f2xx_timer.o
diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c
new file mode 100644
index 0000000..ecadf9d
--- /dev/null
+++ b/hw/timer/stm32f2xx_timer.c
@@ -0,0 +1,328 @@
+/*
+ * STM32F2XX Timer
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/timer/stm32f2xx_timer.h"
+
+#ifndef STM_TIMER_ERR_DEBUG
+#define STM_TIMER_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+ if (STM_TIMER_ERR_DEBUG >= lvl) { \
+ qemu_log("%s: " fmt, __func__, ## args); \
+ } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now);
+
+static void stm32f2xx_timer_interrupt(void *opaque)
+{
+ STM32F2XXTimerState *s = opaque;
+
+ DB_PRINT("Interrupt\n");
+
+ if (s->tim_dier & TIM_DIER_UIE && s->tim_cr1 & TIM_CR1_CEN) {
+ s->tim_sr |= 1;
+ qemu_irq_pulse(s->irq);
+ stm32f2xx_timer_set_alarm(s, s->hit_time);
+ }
+}
+
+static inline int64_t stm32f2xx_ns_to_ticks(STM32F2XXTimerState *s, int64_t t)
+{
+ return muldiv64(t, s->freq_hz, 1000000000ULL) / (s->tim_psc + 1);
+}
+
+static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now)
+{
+ uint64_t ticks;
+ int64_t now_ticks;
+
+ if (s->tim_arr == 0) {
+ return;
+ }
+
+ DB_PRINT("Alarm set at: 0x%x\n", s->tim_cr1);
+
+ now_ticks = stm32f2xx_ns_to_ticks(s, now);
+ ticks = s->tim_arr - (now_ticks - s->tick_offset);
+
+ DB_PRINT("Alarm set in %d ticks\n", (int) ticks);
+
+ s->hit_time = muldiv64((ticks + (uint64_t) now_ticks) * (s->tim_psc + 1),
+ 1000000000ULL, s->freq_hz);
+
+ timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->hit_time);
+ DB_PRINT("Wait Time: %" PRId64 " ticks\n", s->hit_time);
+}
+
+static void stm32f2xx_timer_reset(DeviceState *dev)
+{
+ STM32F2XXTimerState *s = STM32F2XXTIMER(dev);
+ int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+
+ s->tim_cr1 = 0;
+ s->tim_cr2 = 0;
+ s->tim_smcr = 0;
+ s->tim_dier = 0;
+ s->tim_sr = 0;
+ s->tim_egr = 0;
+ s->tim_ccmr1 = 0;
+ s->tim_ccmr2 = 0;
+ s->tim_ccer = 0;
+ s->tim_psc = 0;
+ s->tim_arr = 0;
+ s->tim_ccr1 = 0;
+ s->tim_ccr2 = 0;
+ s->tim_ccr3 = 0;
+ s->tim_ccr4 = 0;
+ s->tim_dcr = 0;
+ s->tim_dmar = 0;
+ s->tim_or = 0;
+
+ s->tick_offset = stm32f2xx_ns_to_ticks(s, now);
+}
+
+static uint64_t stm32f2xx_timer_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ STM32F2XXTimerState *s = opaque;
+
+ DB_PRINT("Read 0x%"HWADDR_PRIx"\n", offset);
+
+ switch (offset) {
+ case TIM_CR1:
+ return s->tim_cr1;
+ case TIM_CR2:
+ return s->tim_cr2;
+ case TIM_SMCR:
+ return s->tim_smcr;
+ case TIM_DIER:
+ return s->tim_dier;
+ case TIM_SR:
+ return s->tim_sr;
+ case TIM_EGR:
+ return s->tim_egr;
+ case TIM_CCMR1:
+ return s->tim_ccmr1;
+ case TIM_CCMR2:
+ return s->tim_ccmr2;
+ case TIM_CCER:
+ return s->tim_ccer;
+ case TIM_CNT:
+ return stm32f2xx_ns_to_ticks(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) -
+ s->tick_offset;
+ case TIM_PSC:
+ return s->tim_psc;
+ case TIM_ARR:
+ return s->tim_arr;
+ case TIM_CCR1:
+ return s->tim_ccr1;
+ case TIM_CCR2:
+ return s->tim_ccr2;
+ case TIM_CCR3:
+ return s->tim_ccr3;
+ case TIM_CCR4:
+ return s->tim_ccr4;
+ case TIM_DCR:
+ return s->tim_dcr;
+ case TIM_DMAR:
+ return s->tim_dmar;
+ case TIM_OR:
+ return s->tim_or;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset);
+ }
+
+ return 0;
+}
+
+static void stm32f2xx_timer_write(void *opaque, hwaddr offset,
+ uint64_t val64, unsigned size)
+{
+ STM32F2XXTimerState *s = opaque;
+ uint32_t value = val64;
+ int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ uint32_t timer_val = 0;
+
+ DB_PRINT("Write 0x%x, 0x%"HWADDR_PRIx"\n", value, offset);
+
+ switch (offset) {
+ case TIM_CR1:
+ s->tim_cr1 = value;
+ return;
+ case TIM_CR2:
+ s->tim_cr2 = value;
+ return;
+ case TIM_SMCR:
+ s->tim_smcr = value;
+ return;
+ case TIM_DIER:
+ s->tim_dier = value;
+ return;
+ case TIM_SR:
+ /* This is set by hardware and cleared by software */
+ s->tim_sr &= value;
+ return;
+ case TIM_EGR:
+ s->tim_egr = value;
+ if (s->tim_egr & TIM_EGR_UG) {
+ timer_val = 0;
+ break;
+ }
+ return;
+ case TIM_CCMR1:
+ s->tim_ccmr1 = value;
+ return;
+ case TIM_CCMR2:
+ s->tim_ccmr2 = value;
+ return;
+ case TIM_CCER:
+ s->tim_ccer = value;
+ return;
+ case TIM_PSC:
+ timer_val = stm32f2xx_ns_to_ticks(s, now) - s->tick_offset;
+ s->tim_psc = value;
+ value = timer_val;
+ break;
+ case TIM_CNT:
+ timer_val = value;
+ break;
+ case TIM_ARR:
+ s->tim_arr = value;
+ stm32f2xx_timer_set_alarm(s, now);
+ return;
+ case TIM_CCR1:
+ s->tim_ccr1 = value;
+ return;
+ case TIM_CCR2:
+ s->tim_ccr2 = value;
+ return;
+ case TIM_CCR3:
+ s->tim_ccr3 = value;
+ return;
+ case TIM_CCR4:
+ s->tim_ccr4 = value;
+ return;
+ case TIM_DCR:
+ s->tim_dcr = value;
+ return;
+ case TIM_DMAR:
+ s->tim_dmar = value;
+ return;
+ case TIM_OR:
+ s->tim_or = value;
+ return;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset);
+ return;
+ }
+
+ /* This means that a register write has affected the timer in a way that
+ * requires a refresh of both tick_offset and the alarm.
+ */
+ s->tick_offset = stm32f2xx_ns_to_ticks(s, now) - timer_val;
+ stm32f2xx_timer_set_alarm(s, now);
+}
+
+static const MemoryRegionOps stm32f2xx_timer_ops = {
+ .read = stm32f2xx_timer_read,
+ .write = stm32f2xx_timer_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static const VMStateDescription vmstate_stm32f2xx_timer = {
+ .name = TYPE_STM32F2XX_TIMER,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_INT64(tick_offset, STM32F2XXTimerState),
+ VMSTATE_UINT32(tim_cr1, STM32F2XXTimerState),
+ VMSTATE_UINT32(tim_cr2, STM32F2XXTimerState),
+ VMSTATE_UINT32(tim_smcr, STM32F2XXTimerState),
+ VMSTATE_UINT32(tim_dier, STM32F2XXTimerState),
+ VMSTATE_UINT32(tim_sr, STM32F2XXTimerState),
+ VMSTATE_UINT32(tim_egr, STM32F2XXTimerState),
+ VMSTATE_UINT32(tim_ccmr1, STM32F2XXTimerState),
+ VMSTATE_UINT32(tim_ccmr2, STM32F2XXTimerState),
+ VMSTATE_UINT32(tim_ccer, STM32F2XXTimerState),
+ VMSTATE_UINT32(tim_psc, STM32F2XXTimerState),
+ VMSTATE_UINT32(tim_arr, STM32F2XXTimerState),
+ VMSTATE_UINT32(tim_ccr1, STM32F2XXTimerState),
+ VMSTATE_UINT32(tim_ccr2, STM32F2XXTimerState),
+ VMSTATE_UINT32(tim_ccr3, STM32F2XXTimerState),
+ VMSTATE_UINT32(tim_ccr4, STM32F2XXTimerState),
+ VMSTATE_UINT32(tim_dcr, STM32F2XXTimerState),
+ VMSTATE_UINT32(tim_dmar, STM32F2XXTimerState),
+ VMSTATE_UINT32(tim_or, STM32F2XXTimerState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static Property stm32f2xx_timer_properties[] = {
+ DEFINE_PROP_UINT64("clock-frequency", struct STM32F2XXTimerState,
+ freq_hz, 1000000000),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void stm32f2xx_timer_init(Object *obj)
+{
+ STM32F2XXTimerState *s = STM32F2XXTIMER(obj);
+
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
+
+ memory_region_init_io(&s->iomem, obj, &stm32f2xx_timer_ops, s,
+ "stm32f2xx_timer", 0x4000);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
+
+ s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f2xx_timer_interrupt, s);
+}
+
+static void stm32f2xx_timer_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = stm32f2xx_timer_reset;
+ dc->props = stm32f2xx_timer_properties;
+ dc->vmsd = &vmstate_stm32f2xx_timer;
+}
+
+static const TypeInfo stm32f2xx_timer_info = {
+ .name = TYPE_STM32F2XX_TIMER,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(STM32F2XXTimerState),
+ .instance_init = stm32f2xx_timer_init,
+ .class_init = stm32f2xx_timer_class_init,
+};
+
+static void stm32f2xx_timer_register_types(void)
+{
+ type_register_static(&stm32f2xx_timer_info);
+}
+
+type_init(stm32f2xx_timer_register_types)
diff --git a/include/hw/timer/stm32f2xx_timer.h b/include/hw/timer/stm32f2xx_timer.h
new file mode 100644
index 0000000..e6a8323
--- /dev/null
+++ b/include/hw/timer/stm32f2xx_timer.h
@@ -0,0 +1,101 @@
+/*
+ * STM32F2XX Timer
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_STM32F2XX_TIMER_H
+#define HW_STM32F2XX_TIMER_H
+
+#include "hw/sysbus.h"
+#include "qemu/timer.h"
+#include "sysemu/sysemu.h"
+
+#define TIM_CR1 0x00
+#define TIM_CR2 0x04
+#define TIM_SMCR 0x08
+#define TIM_DIER 0x0C
+#define TIM_SR 0x10
+#define TIM_EGR 0x14
+#define TIM_CCMR1 0x18
+#define TIM_CCMR2 0x1C
+#define TIM_CCER 0x20
+#define TIM_CNT 0x24
+#define TIM_PSC 0x28
+#define TIM_ARR 0x2C
+#define TIM_CCR1 0x34
+#define TIM_CCR2 0x38
+#define TIM_CCR3 0x3C
+#define TIM_CCR4 0x40
+#define TIM_DCR 0x48
+#define TIM_DMAR 0x4C
+#define TIM_OR 0x50
+
+#define TIM_CR1_CEN 1
+
+#define TIM_EGR_UG 1
+
+#define TIM_CCER_CC2E (1 << 4)
+#define TIM_CCMR1_OC2M2 (1 << 14)
+#define TIM_CCMR1_OC2M1 (1 << 13)
+#define TIM_CCMR1_OC2M0 (1 << 12)
+#define TIM_CCMR1_OC2PE (1 << 11)
+
+#define TIM_DIER_UIE 1
+
+#define TYPE_STM32F2XX_TIMER "stm32f2xx-timer"
+#define STM32F2XXTIMER(obj) OBJECT_CHECK(STM32F2XXTimerState, \
+ (obj), TYPE_STM32F2XX_TIMER)
+
+typedef struct STM32F2XXTimerState {
+ /* <private> */
+ SysBusDevice parent_obj;
+
+ /* <public> */
+ MemoryRegion iomem;
+ QEMUTimer *timer;
+ qemu_irq irq;
+
+ int64_t tick_offset;
+ uint64_t hit_time;
+ uint64_t freq_hz;
+
+ uint32_t tim_cr1;
+ uint32_t tim_cr2;
+ uint32_t tim_smcr;
+ uint32_t tim_dier;
+ uint32_t tim_sr;
+ uint32_t tim_egr;
+ uint32_t tim_ccmr1;
+ uint32_t tim_ccmr2;
+ uint32_t tim_ccer;
+ uint32_t tim_psc;
+ uint32_t tim_arr;
+ uint32_t tim_ccr1;
+ uint32_t tim_ccr2;
+ uint32_t tim_ccr3;
+ uint32_t tim_ccr4;
+ uint32_t tim_dcr;
+ uint32_t tim_dmar;
+ uint32_t tim_or;
+} STM32F2XXTimerState;
+
+#endif /* HW_STM32F2XX_TIMER_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PULL 03/10] stm32f2xx_USART: Add the stm32f2xx USART Controller
2015-03-11 14:18 [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell
2015-03-11 14:18 ` [Qemu-devel] [PULL 01/10] hw/arm/virt: fix cmdline parsing bug with CPU options and smp > 1 Peter Maydell
2015-03-11 14:18 ` [Qemu-devel] [PULL 02/10] stm32f2xx_timer: Add the stm32f2xx Timer Peter Maydell
@ 2015-03-11 14:18 ` Peter Maydell
2015-03-11 14:18 ` [Qemu-devel] [PULL 04/10] stm32f2xx_SYSCFG: Add the stm32f2xx SYSCFG Peter Maydell
` (7 subsequent siblings)
10 siblings, 0 replies; 32+ messages in thread
From: Peter Maydell @ 2015-03-11 14:18 UTC (permalink / raw)
To: qemu-devel
From: Alistair Francis <alistair23@gmail.com>
This patch adds the stm32f2xx USART controller
(UART also uses the same controller).
Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 762c6c0d2a41d574932bc4445ec9bfffe6da8798.1424175342.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
default-configs/arm-softmmu.mak | 1 +
hw/char/Makefile.objs | 1 +
hw/char/stm32f2xx_usart.c | 229 ++++++++++++++++++++++++++++++++++++++
include/hw/char/stm32f2xx_usart.h | 73 ++++++++++++
4 files changed, 304 insertions(+)
create mode 100644 hw/char/stm32f2xx_usart.c
create mode 100644 include/hw/char/stm32f2xx_usart.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index bdb6eeb..e2100b7 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -81,6 +81,7 @@ CONFIG_REALVIEW=y
CONFIG_ZAURUS=y
CONFIG_ZYNQ=y
CONFIG_STM32F2XX_TIMER=y
+CONFIG_STM32F2XX_USART=y
CONFIG_VERSATILE_PCI=y
CONFIG_VERSATILE_I2C=y
diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs
index 317385d..5931cc8 100644
--- a/hw/char/Makefile.objs
+++ b/hw/char/Makefile.objs
@@ -15,6 +15,7 @@ obj-$(CONFIG_OMAP) += omap_uart.o
obj-$(CONFIG_SH4) += sh_serial.o
obj-$(CONFIG_PSERIES) += spapr_vty.o
obj-$(CONFIG_DIGIC) += digic-uart.o
+obj-$(CONFIG_STM32F2XX_USART) += stm32f2xx_usart.o
common-obj-$(CONFIG_ETRAXFS) += etraxfs_ser.o
common-obj-$(CONFIG_ISA_DEBUG) += debugcon.o
diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c
new file mode 100644
index 0000000..260b053
--- /dev/null
+++ b/hw/char/stm32f2xx_usart.c
@@ -0,0 +1,229 @@
+/*
+ * STM32F2XX USART
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/char/stm32f2xx_usart.h"
+
+#ifndef STM_USART_ERR_DEBUG
+#define STM_USART_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+ if (STM_USART_ERR_DEBUG >= lvl) { \
+ qemu_log("%s: " fmt, __func__, ## args); \
+ } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static int stm32f2xx_usart_can_receive(void *opaque)
+{
+ STM32F2XXUsartState *s = opaque;
+
+ if (!(s->usart_sr & USART_SR_RXNE)) {
+ return 1;
+ }
+
+ return 0;
+}
+
+static void stm32f2xx_usart_receive(void *opaque, const uint8_t *buf, int size)
+{
+ STM32F2XXUsartState *s = opaque;
+
+ s->usart_dr = *buf;
+
+ if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) {
+ /* USART not enabled - drop the chars */
+ DB_PRINT("Dropping the chars\n");
+ return;
+ }
+
+ s->usart_sr |= USART_SR_RXNE;
+
+ if (s->usart_cr1 & USART_CR1_RXNEIE) {
+ qemu_set_irq(s->irq, 1);
+ }
+
+ DB_PRINT("Receiving: %c\n", s->usart_dr);
+}
+
+static void stm32f2xx_usart_reset(DeviceState *dev)
+{
+ STM32F2XXUsartState *s = STM32F2XX_USART(dev);
+
+ s->usart_sr = USART_SR_RESET;
+ s->usart_dr = 0x00000000;
+ s->usart_brr = 0x00000000;
+ s->usart_cr1 = 0x00000000;
+ s->usart_cr2 = 0x00000000;
+ s->usart_cr3 = 0x00000000;
+ s->usart_gtpr = 0x00000000;
+
+ qemu_set_irq(s->irq, 0);
+}
+
+static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ STM32F2XXUsartState *s = opaque;
+ uint64_t retvalue;
+
+ DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr);
+
+ switch (addr) {
+ case USART_SR:
+ retvalue = s->usart_sr;
+ s->usart_sr &= ~USART_SR_TC;
+ if (s->chr) {
+ qemu_chr_accept_input(s->chr);
+ }
+ return retvalue;
+ case USART_DR:
+ DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr);
+ s->usart_sr |= USART_SR_TXE;
+ s->usart_sr &= ~USART_SR_RXNE;
+ if (s->chr) {
+ qemu_chr_accept_input(s->chr);
+ }
+ qemu_set_irq(s->irq, 0);
+ return s->usart_dr & 0x3FF;
+ case USART_BRR:
+ return s->usart_brr;
+ case USART_CR1:
+ return s->usart_cr1;
+ case USART_CR2:
+ return s->usart_cr2;
+ case USART_CR3:
+ return s->usart_cr3;
+ case USART_GTPR:
+ return s->usart_gtpr;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+ return 0;
+ }
+
+ return 0;
+}
+
+static void stm32f2xx_usart_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
+{
+ STM32F2XXUsartState *s = opaque;
+ uint32_t value = val64;
+ unsigned char ch;
+
+ DB_PRINT("Write 0x%" PRIx32 ", 0x%"HWADDR_PRIx"\n", value, addr);
+
+ switch (addr) {
+ case USART_SR:
+ if (value <= 0x3FF) {
+ s->usart_sr = value;
+ } else {
+ s->usart_sr &= value;
+ }
+ if (!(s->usart_sr & USART_SR_RXNE)) {
+ qemu_set_irq(s->irq, 0);
+ }
+ return;
+ case USART_DR:
+ if (value < 0xF000) {
+ ch = value;
+ if (s->chr) {
+ qemu_chr_fe_write_all(s->chr, &ch, 1);
+ }
+ s->usart_sr |= USART_SR_TC;
+ s->usart_sr &= ~USART_SR_TXE;
+ }
+ return;
+ case USART_BRR:
+ s->usart_brr = value;
+ return;
+ case USART_CR1:
+ s->usart_cr1 = value;
+ if (s->usart_cr1 & USART_CR1_RXNEIE &&
+ s->usart_sr & USART_SR_RXNE) {
+ qemu_set_irq(s->irq, 1);
+ }
+ return;
+ case USART_CR2:
+ s->usart_cr2 = value;
+ return;
+ case USART_CR3:
+ s->usart_cr3 = value;
+ return;
+ case USART_GTPR:
+ s->usart_gtpr = value;
+ return;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+ }
+}
+
+static const MemoryRegionOps stm32f2xx_usart_ops = {
+ .read = stm32f2xx_usart_read,
+ .write = stm32f2xx_usart_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void stm32f2xx_usart_init(Object *obj)
+{
+ STM32F2XXUsartState *s = STM32F2XX_USART(obj);
+
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
+
+ memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s,
+ TYPE_STM32F2XX_USART, 0x2000);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+
+ s->chr = qemu_char_get_next_serial();
+
+ if (s->chr) {
+ qemu_chr_add_handlers(s->chr, stm32f2xx_usart_can_receive,
+ stm32f2xx_usart_receive, NULL, s);
+ }
+}
+
+static void stm32f2xx_usart_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = stm32f2xx_usart_reset;
+}
+
+static const TypeInfo stm32f2xx_usart_info = {
+ .name = TYPE_STM32F2XX_USART,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(STM32F2XXUsartState),
+ .instance_init = stm32f2xx_usart_init,
+ .class_init = stm32f2xx_usart_class_init,
+};
+
+static void stm32f2xx_usart_register_types(void)
+{
+ type_register_static(&stm32f2xx_usart_info);
+}
+
+type_init(stm32f2xx_usart_register_types)
diff --git a/include/hw/char/stm32f2xx_usart.h b/include/hw/char/stm32f2xx_usart.h
new file mode 100644
index 0000000..b97f192
--- /dev/null
+++ b/include/hw/char/stm32f2xx_usart.h
@@ -0,0 +1,73 @@
+/*
+ * STM32F2XX USART
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_STM32F2XX_USART_H
+#define HW_STM32F2XX_USART_H
+
+#include "hw/sysbus.h"
+#include "sysemu/char.h"
+#include "hw/hw.h"
+
+#define USART_SR 0x00
+#define USART_DR 0x04
+#define USART_BRR 0x08
+#define USART_CR1 0x0C
+#define USART_CR2 0x10
+#define USART_CR3 0x14
+#define USART_GTPR 0x18
+
+#define USART_SR_RESET 0x00C00000
+
+#define USART_SR_TXE (1 << 7)
+#define USART_SR_TC (1 << 6)
+#define USART_SR_RXNE (1 << 5)
+
+#define USART_CR1_UE (1 << 13)
+#define USART_CR1_RXNEIE (1 << 5)
+#define USART_CR1_TE (1 << 3)
+#define USART_CR1_RE (1 << 2)
+
+#define TYPE_STM32F2XX_USART "stm32f2xx-usart"
+#define STM32F2XX_USART(obj) \
+ OBJECT_CHECK(STM32F2XXUsartState, (obj), TYPE_STM32F2XX_USART)
+
+typedef struct {
+ /* <private> */
+ SysBusDevice parent_obj;
+
+ /* <public> */
+ MemoryRegion mmio;
+
+ uint32_t usart_sr;
+ uint32_t usart_dr;
+ uint32_t usart_brr;
+ uint32_t usart_cr1;
+ uint32_t usart_cr2;
+ uint32_t usart_cr3;
+ uint32_t usart_gtpr;
+
+ CharDriverState *chr;
+ qemu_irq irq;
+} STM32F2XXUsartState;
+#endif /* HW_STM32F2XX_USART_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PULL 04/10] stm32f2xx_SYSCFG: Add the stm32f2xx SYSCFG
2015-03-11 14:18 [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell
` (2 preceding siblings ...)
2015-03-11 14:18 ` [Qemu-devel] [PULL 03/10] stm32f2xx_USART: Add the stm32f2xx USART Controller Peter Maydell
@ 2015-03-11 14:18 ` Peter Maydell
2015-03-11 14:18 ` [Qemu-devel] [PULL 05/10] stm32f205: Add the stm32f205 SoC Peter Maydell
` (6 subsequent siblings)
10 siblings, 0 replies; 32+ messages in thread
From: Peter Maydell @ 2015-03-11 14:18 UTC (permalink / raw)
To: qemu-devel
From: Alistair Francis <alistair23@gmail.com>
This patch adds the stm32f2xx System Configuration
Controller. This is used to configure what memory is mapped
at address 0 (although that is not supported) as well
as configure how the EXTI interrupts work (also not
supported at the moment).
This device is not required for basic examples, but more
complex systems will require it (as well as the EXTI device)
Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 5d499d7b60b61d5d6dcb310b2e55411b1f53794e.1424175342.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
default-configs/arm-softmmu.mak | 1 +
hw/misc/Makefile.objs | 1 +
hw/misc/stm32f2xx_syscfg.c | 160 +++++++++++++++++++++++++++++++++++++
include/hw/misc/stm32f2xx_syscfg.h | 61 ++++++++++++++
4 files changed, 223 insertions(+)
create mode 100644 hw/misc/stm32f2xx_syscfg.c
create mode 100644 include/hw/misc/stm32f2xx_syscfg.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index e2100b7..669dc59 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -82,6 +82,7 @@ CONFIG_ZAURUS=y
CONFIG_ZYNQ=y
CONFIG_STM32F2XX_TIMER=y
CONFIG_STM32F2XX_USART=y
+CONFIG_STM32F2XX_SYSCFG=y
CONFIG_VERSATILE_PCI=y
CONFIG_VERSATILE_I2C=y
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 6c6e296..4aa76ff 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -36,6 +36,7 @@ obj-$(CONFIG_OMAP) += omap_sdrc.o
obj-$(CONFIG_OMAP) += omap_tap.o
obj-$(CONFIG_SLAVIO) += slavio_misc.o
obj-$(CONFIG_ZYNQ) += zynq_slcr.o
+obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
obj-$(CONFIG_PVPANIC) += pvpanic.o
obj-$(CONFIG_EDU) += edu.o
diff --git a/hw/misc/stm32f2xx_syscfg.c b/hw/misc/stm32f2xx_syscfg.c
new file mode 100644
index 0000000..4ae4042
--- /dev/null
+++ b/hw/misc/stm32f2xx_syscfg.c
@@ -0,0 +1,160 @@
+/*
+ * STM32F2XX SYSCFG
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/misc/stm32f2xx_syscfg.h"
+
+#ifndef STM_SYSCFG_ERR_DEBUG
+#define STM_SYSCFG_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+ if (STM_SYSCFG_ERR_DEBUG >= lvl) { \
+ qemu_log("%s: " fmt, __func__, ## args); \
+ } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static void stm32f2xx_syscfg_reset(DeviceState *dev)
+{
+ STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(dev);
+
+ s->syscfg_memrmp = 0x00000000;
+ s->syscfg_pmc = 0x00000000;
+ s->syscfg_exticr1 = 0x00000000;
+ s->syscfg_exticr2 = 0x00000000;
+ s->syscfg_exticr3 = 0x00000000;
+ s->syscfg_exticr4 = 0x00000000;
+ s->syscfg_cmpcr = 0x00000000;
+}
+
+static uint64_t stm32f2xx_syscfg_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ STM32F2XXSyscfgState *s = opaque;
+
+ DB_PRINT("0x%"HWADDR_PRIx"\n", addr);
+
+ switch (addr) {
+ case SYSCFG_MEMRMP:
+ return s->syscfg_memrmp;
+ case SYSCFG_PMC:
+ return s->syscfg_pmc;
+ case SYSCFG_EXTICR1:
+ return s->syscfg_exticr1;
+ case SYSCFG_EXTICR2:
+ return s->syscfg_exticr2;
+ case SYSCFG_EXTICR3:
+ return s->syscfg_exticr3;
+ case SYSCFG_EXTICR4:
+ return s->syscfg_exticr4;
+ case SYSCFG_CMPCR:
+ return s->syscfg_cmpcr;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+ return 0;
+ }
+
+ return 0;
+}
+
+static void stm32f2xx_syscfg_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
+{
+ STM32F2XXSyscfgState *s = opaque;
+ uint32_t value = val64;
+
+ DB_PRINT("0x%x, 0x%"HWADDR_PRIx"\n", value, addr);
+
+ switch (addr) {
+ case SYSCFG_MEMRMP:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Changeing the memory mapping isn't supported " \
+ "in QEMU\n", __func__);
+ return;
+ case SYSCFG_PMC:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Changeing the memory mapping isn't supported " \
+ "in QEMU\n", __func__);
+ return;
+ case SYSCFG_EXTICR1:
+ s->syscfg_exticr1 = (value & 0xFFFF);
+ return;
+ case SYSCFG_EXTICR2:
+ s->syscfg_exticr2 = (value & 0xFFFF);
+ return;
+ case SYSCFG_EXTICR3:
+ s->syscfg_exticr3 = (value & 0xFFFF);
+ return;
+ case SYSCFG_EXTICR4:
+ s->syscfg_exticr4 = (value & 0xFFFF);
+ return;
+ case SYSCFG_CMPCR:
+ s->syscfg_cmpcr = value;
+ return;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+ }
+}
+
+static const MemoryRegionOps stm32f2xx_syscfg_ops = {
+ .read = stm32f2xx_syscfg_read,
+ .write = stm32f2xx_syscfg_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void stm32f2xx_syscfg_init(Object *obj)
+{
+ STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(obj);
+
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
+
+ memory_region_init_io(&s->mmio, obj, &stm32f2xx_syscfg_ops, s,
+ TYPE_STM32F2XX_SYSCFG, 0x400);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+}
+
+static void stm32f2xx_syscfg_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = stm32f2xx_syscfg_reset;
+}
+
+static const TypeInfo stm32f2xx_syscfg_info = {
+ .name = TYPE_STM32F2XX_SYSCFG,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(STM32F2XXSyscfgState),
+ .instance_init = stm32f2xx_syscfg_init,
+ .class_init = stm32f2xx_syscfg_class_init,
+};
+
+static void stm32f2xx_syscfg_register_types(void)
+{
+ type_register_static(&stm32f2xx_syscfg_info);
+}
+
+type_init(stm32f2xx_syscfg_register_types)
diff --git a/include/hw/misc/stm32f2xx_syscfg.h b/include/hw/misc/stm32f2xx_syscfg.h
new file mode 100644
index 0000000..69e6a30
--- /dev/null
+++ b/include/hw/misc/stm32f2xx_syscfg.h
@@ -0,0 +1,61 @@
+/*
+ * STM32F2XX SYSCFG
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_STM32F2XX_SYSCFG_H
+#define HW_STM32F2XX_SYSCFG_H
+
+#include "hw/sysbus.h"
+#include "hw/hw.h"
+
+#define SYSCFG_MEMRMP 0x00
+#define SYSCFG_PMC 0x04
+#define SYSCFG_EXTICR1 0x08
+#define SYSCFG_EXTICR2 0x0C
+#define SYSCFG_EXTICR3 0x10
+#define SYSCFG_EXTICR4 0x14
+#define SYSCFG_CMPCR 0x20
+
+#define TYPE_STM32F2XX_SYSCFG "stm32f2xx-syscfg"
+#define STM32F2XX_SYSCFG(obj) \
+ OBJECT_CHECK(STM32F2XXSyscfgState, (obj), TYPE_STM32F2XX_SYSCFG)
+
+typedef struct {
+ /* <private> */
+ SysBusDevice parent_obj;
+
+ /* <public> */
+ MemoryRegion mmio;
+
+ uint32_t syscfg_memrmp;
+ uint32_t syscfg_pmc;
+ uint32_t syscfg_exticr1;
+ uint32_t syscfg_exticr2;
+ uint32_t syscfg_exticr3;
+ uint32_t syscfg_exticr4;
+ uint32_t syscfg_cmpcr;
+
+ qemu_irq irq;
+} STM32F2XXSyscfgState;
+
+#endif /* HW_STM32F2XX_SYSCFG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PULL 05/10] stm32f205: Add the stm32f205 SoC
2015-03-11 14:18 [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell
` (3 preceding siblings ...)
2015-03-11 14:18 ` [Qemu-devel] [PULL 04/10] stm32f2xx_SYSCFG: Add the stm32f2xx SYSCFG Peter Maydell
@ 2015-03-11 14:18 ` Peter Maydell
2015-03-11 14:18 ` [Qemu-devel] [PULL 06/10] netduino2: Add the Netduino 2 Machine Peter Maydell
` (5 subsequent siblings)
10 siblings, 0 replies; 32+ messages in thread
From: Peter Maydell @ 2015-03-11 14:18 UTC (permalink / raw)
To: qemu-devel
From: Alistair Francis <alistair23@gmail.com>
This patch adds the stm32f205 SoC. This will be used by the
Netduino 2 to create a machine.
Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 48d509747a1ea0d8a7d5480560495e679990f9d2.1424175342.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
default-configs/arm-softmmu.mak | 1 +
hw/arm/Makefile.objs | 1 +
hw/arm/stm32f205_soc.c | 160 ++++++++++++++++++++++++++++++++++++++++
include/hw/arm/stm32f205_soc.h | 57 ++++++++++++++
4 files changed, 219 insertions(+)
create mode 100644 hw/arm/stm32f205_soc.c
create mode 100644 include/hw/arm/stm32f205_soc.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 669dc59..87d4e34 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -83,6 +83,7 @@ CONFIG_ZYNQ=y
CONFIG_STM32F2XX_TIMER=y
CONFIG_STM32F2XX_USART=y
CONFIG_STM32F2XX_SYSCFG=y
+CONFIG_STM32F205_SOC=y
CONFIG_VERSATILE_PCI=y
CONFIG_VERSATILE_I2C=y
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 6088e53..9769317 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -8,3 +8,4 @@ obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
obj-$(CONFIG_DIGIC) += digic.o
obj-y += omap1.o omap2.o strongarm.o
obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
+obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
new file mode 100644
index 0000000..0f3bdc7
--- /dev/null
+++ b/hw/arm/stm32f205_soc.c
@@ -0,0 +1,160 @@
+/*
+ * STM32F205 SoC
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/arm/arm.h"
+#include "exec/address-spaces.h"
+#include "hw/arm/stm32f205_soc.h"
+
+/* At the moment only Timer 2 to 5 are modelled */
+static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
+ 0x40000800, 0x40000C00 };
+static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
+ 0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
+
+static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
+static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
+
+static void stm32f205_soc_initfn(Object *obj)
+{
+ STM32F205State *s = STM32F205_SOC(obj);
+ int i;
+
+ object_initialize(&s->syscfg, sizeof(s->syscfg), TYPE_STM32F2XX_SYSCFG);
+ qdev_set_parent_bus(DEVICE(&s->syscfg), sysbus_get_default());
+
+ for (i = 0; i < STM_NUM_USARTS; i++) {
+ object_initialize(&s->usart[i], sizeof(s->usart[i]),
+ TYPE_STM32F2XX_USART);
+ qdev_set_parent_bus(DEVICE(&s->usart[i]), sysbus_get_default());
+ }
+
+ for (i = 0; i < STM_NUM_TIMERS; i++) {
+ object_initialize(&s->timer[i], sizeof(s->timer[i]),
+ TYPE_STM32F2XX_TIMER);
+ qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default());
+ }
+}
+
+static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
+{
+ STM32F205State *s = STM32F205_SOC(dev_soc);
+ DeviceState *syscfgdev, *usartdev, *timerdev;
+ SysBusDevice *syscfgbusdev, *usartbusdev, *timerbusdev;
+ qemu_irq *pic;
+ Error *err = NULL;
+ int i;
+
+ MemoryRegion *system_memory = get_system_memory();
+ MemoryRegion *sram = g_new(MemoryRegion, 1);
+ MemoryRegion *flash = g_new(MemoryRegion, 1);
+ MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
+
+ memory_region_init_ram(flash, NULL, "STM32F205.flash", FLASH_SIZE,
+ &error_abort);
+ memory_region_init_alias(flash_alias, NULL, "STM32F205.flash.alias",
+ flash, 0, FLASH_SIZE);
+
+ vmstate_register_ram_global(flash);
+
+ memory_region_set_readonly(flash, true);
+ memory_region_set_readonly(flash_alias, true);
+
+ memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
+ memory_region_add_subregion(system_memory, 0, flash_alias);
+
+ memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE,
+ &error_abort);
+ vmstate_register_ram_global(sram);
+ memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
+
+ pic = armv7m_init(get_system_memory(), FLASH_SIZE, 96,
+ s->kernel_filename, s->cpu_model);
+
+ /* System configuration controller */
+ syscfgdev = DEVICE(&s->syscfg);
+ object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ syscfgbusdev = SYS_BUS_DEVICE(syscfgdev);
+ sysbus_mmio_map(syscfgbusdev, 0, 0x40013800);
+ sysbus_connect_irq(syscfgbusdev, 0, pic[71]);
+
+ /* Attach UART (uses USART registers) and USART controllers */
+ for (i = 0; i < STM_NUM_USARTS; i++) {
+ usartdev = DEVICE(&(s->usart[i]));
+ object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ usartbusdev = SYS_BUS_DEVICE(usartdev);
+ sysbus_mmio_map(usartbusdev, 0, usart_addr[i]);
+ sysbus_connect_irq(usartbusdev, 0, pic[usart_irq[i]]);
+ }
+
+ /* Timer 2 to 5 */
+ for (i = 0; i < STM_NUM_TIMERS; i++) {
+ timerdev = DEVICE(&(s->timer[i]));
+ qdev_prop_set_uint64(timerdev, "clock-frequency", 1000000000);
+ object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ timerbusdev = SYS_BUS_DEVICE(timerdev);
+ sysbus_mmio_map(timerbusdev, 0, timer_addr[i]);
+ sysbus_connect_irq(timerbusdev, 0, pic[timer_irq[i]]);
+ }
+}
+
+static Property stm32f205_soc_properties[] = {
+ DEFINE_PROP_STRING("kernel-filename", STM32F205State, kernel_filename),
+ DEFINE_PROP_STRING("cpu-model", STM32F205State, cpu_model),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void stm32f205_soc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = stm32f205_soc_realize;
+ dc->props = stm32f205_soc_properties;
+}
+
+static const TypeInfo stm32f205_soc_info = {
+ .name = TYPE_STM32F205_SOC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(STM32F205State),
+ .instance_init = stm32f205_soc_initfn,
+ .class_init = stm32f205_soc_class_init,
+};
+
+static void stm32f205_soc_types(void)
+{
+ type_register_static(&stm32f205_soc_info);
+}
+
+type_init(stm32f205_soc_types)
diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
new file mode 100644
index 0000000..3cda170
--- /dev/null
+++ b/include/hw/arm/stm32f205_soc.h
@@ -0,0 +1,57 @@
+/*
+ * STM32F205 SoC
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_ARM_STM32F205SOC_H
+#define HW_ARM_STM32F205SOC_H
+
+#include "hw/misc/stm32f2xx_syscfg.h"
+#include "hw/timer/stm32f2xx_timer.h"
+#include "hw/char/stm32f2xx_usart.h"
+
+#define TYPE_STM32F205_SOC "stm32f205_soc"
+#define STM32F205_SOC(obj) \
+ OBJECT_CHECK(STM32F205State, (obj), TYPE_STM32F205_SOC)
+
+#define STM_NUM_USARTS 6
+#define STM_NUM_TIMERS 4
+
+#define FLASH_BASE_ADDRESS 0x08000000
+#define FLASH_SIZE (1024 * 1024)
+#define SRAM_BASE_ADDRESS 0x20000000
+#define SRAM_SIZE (128 * 1024)
+
+typedef struct STM32F205State {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ char *kernel_filename;
+ char *cpu_model;
+
+ STM32F2XXSyscfgState syscfg;
+ STM32F2XXUsartState usart[STM_NUM_USARTS];
+ STM32F2XXTimerState timer[STM_NUM_TIMERS];
+} STM32F205State;
+
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PULL 06/10] netduino2: Add the Netduino 2 Machine
2015-03-11 14:18 [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell
` (4 preceding siblings ...)
2015-03-11 14:18 ` [Qemu-devel] [PULL 05/10] stm32f205: Add the stm32f205 SoC Peter Maydell
@ 2015-03-11 14:18 ` Peter Maydell
2015-03-11 14:18 ` [Qemu-devel] [PULL 07/10] target-arm: Add missing compatible property to A57 Peter Maydell
` (4 subsequent siblings)
10 siblings, 0 replies; 32+ messages in thread
From: Peter Maydell @ 2015-03-11 14:18 UTC (permalink / raw)
To: qemu-devel
From: Alistair Francis <alistair23@gmail.com>
This patch adds the Netduino 2 Machine.
This is a Cortex-M3 based machine. Information can be found at:
http://www.netduino.com/netduino2/specs.htm
Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 5bd999824f14252c122c4501cc973cee986eadd7.1424175342.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/Makefile.objs | 1 +
hw/arm/netduino2.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 58 insertions(+)
create mode 100644 hw/arm/netduino2.c
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 9769317..2577f68 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -3,6 +3,7 @@ obj-$(CONFIG_DIGIC) += digic_boards.o
obj-y += integratorcp.o kzm.o mainstone.o musicpal.o nseries.o
obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o
obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
+obj-y += netduino2.o
obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
obj-$(CONFIG_DIGIC) += digic.o
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
new file mode 100644
index 0000000..8f26780
--- /dev/null
+++ b/hw/arm/netduino2.c
@@ -0,0 +1,57 @@
+/*
+ * Netduino 2 Machine Model
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/boards.h"
+#include "qemu/error-report.h"
+#include "hw/arm/stm32f205_soc.h"
+
+static void netduino2_init(MachineState *machine)
+{
+ DeviceState *dev;
+ Error *err = NULL;
+
+ dev = qdev_create(NULL, TYPE_STM32F205_SOC);
+ if (machine->kernel_filename) {
+ qdev_prop_set_string(dev, "kernel-filename", machine->kernel_filename);
+ }
+ qdev_prop_set_string(dev, "cpu-model", "cortex-m3");
+ object_property_set_bool(OBJECT(dev), true, "realized", &err);
+ if (err != NULL) {
+ error_report("%s", error_get_pretty(err));
+ exit(1);
+ }
+}
+
+static QEMUMachine netduino2_machine = {
+ .name = "netduino2",
+ .desc = "Netduino 2 Machine",
+ .init = netduino2_init,
+};
+
+static void netduino2_machine_init(void)
+{
+ qemu_register_machine(&netduino2_machine);
+}
+
+machine_init(netduino2_machine_init);
--
1.9.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PULL 07/10] target-arm: Add missing compatible property to A57
2015-03-11 14:18 [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell
` (5 preceding siblings ...)
2015-03-11 14:18 ` [Qemu-devel] [PULL 06/10] netduino2: Add the Netduino 2 Machine Peter Maydell
@ 2015-03-11 14:18 ` Peter Maydell
2015-03-11 14:18 ` [Qemu-devel] [PULL 08/10] integrator/cp: Model CP control registers as sysbus device Peter Maydell
` (3 subsequent siblings)
10 siblings, 0 replies; 32+ messages in thread
From: Peter Maydell @ 2015-03-11 14:18 UTC (permalink / raw)
To: qemu-devel
From: Ryota Ozaki <ozaki.ryota@gmail.com>
Signed-off-by: Ryota Ozaki <ozaki.ryota@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1424097799-11002-1-git-send-email-ozaki.ryota@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index 823c739..270bc2f 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -96,6 +96,7 @@ static void aarch64_a57_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ cpu->dtb_compatible = "arm,cortex-a57";
set_feature(&cpu->env, ARM_FEATURE_V8);
set_feature(&cpu->env, ARM_FEATURE_VFP4);
set_feature(&cpu->env, ARM_FEATURE_NEON);
--
1.9.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PULL 08/10] integrator/cp: Model CP control registers as sysbus device
2015-03-11 14:18 [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell
` (6 preceding siblings ...)
2015-03-11 14:18 ` [Qemu-devel] [PULL 07/10] target-arm: Add missing compatible property to A57 Peter Maydell
@ 2015-03-11 14:18 ` Peter Maydell
2015-03-11 14:18 ` [Qemu-devel] [PULL 09/10] integrator/cp: Implement CARDIN and WPROT signals Peter Maydell
` (2 subsequent siblings)
10 siblings, 0 replies; 32+ messages in thread
From: Peter Maydell @ 2015-03-11 14:18 UTC (permalink / raw)
To: qemu-devel
From: Jan Kiszka <jan.kiszka@siemens.com>
No new features yet, just encapsulation.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Message-id: 3829c7c7e01cd3ccf15a1198f114e4d675974ae0.1426004843.git.jan.kiszka@siemens.com
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/integratorcp.c | 35 +++++++++++++++++++++++++++--------
1 file changed, 27 insertions(+), 8 deletions(-)
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index 949ae1e..0dbda3a 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -406,6 +406,18 @@ static int icp_pic_init(SysBusDevice *sbd)
/* CP control registers. */
+#define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs"
+#define ICP_CONTROL_REGS(obj) \
+ OBJECT_CHECK(ICPCtrlRegsState, (obj), TYPE_ICP_CONTROL_REGS)
+
+typedef struct ICPCtrlRegsState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ MemoryRegion iomem;
+} ICPCtrlRegsState;
+
static uint64_t icp_control_read(void *opaque, hwaddr offset,
unsigned size)
{
@@ -444,15 +456,14 @@ static const MemoryRegionOps icp_control_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void icp_control_init(hwaddr base)
+static void icp_control_init(Object *obj)
{
- MemoryRegion *io;
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ ICPCtrlRegsState *s = ICP_CONTROL_REGS(obj);
- io = (MemoryRegion *)g_malloc0(sizeof(MemoryRegion));
- memory_region_init_io(io, NULL, &icp_control_ops, NULL,
- "control", 0x00800000);
- memory_region_add_subregion(get_system_memory(), base, io);
- /* ??? Save/restore. */
+ memory_region_init_io(&s->iomem, OBJECT(s), &icp_control_ops, s,
+ "icp_ctrl_regs", 0x00800000);
+ sysbus_init_mmio(sbd, &s->iomem);
}
@@ -541,7 +552,7 @@ static void integratorcp_init(MachineState *machine)
sysbus_create_simple("pl031", 0x15000000, pic[8]);
sysbus_create_simple("pl011", 0x16000000, pic[1]);
sysbus_create_simple("pl011", 0x17000000, pic[2]);
- icp_control_init(0xcb000000);
+ sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000, NULL);
sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]);
sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]);
sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0);
@@ -606,10 +617,18 @@ static const TypeInfo icp_pic_info = {
.class_init = icp_pic_class_init,
};
+static const TypeInfo icp_ctrl_regs_info = {
+ .name = TYPE_ICP_CONTROL_REGS,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(ICPCtrlRegsState),
+ .instance_init = icp_control_init,
+};
+
static void integratorcp_register_types(void)
{
type_register_static(&icp_pic_info);
type_register_static(&core_info);
+ type_register_static(&icp_ctrl_regs_info);
}
type_init(integratorcp_register_types)
--
1.9.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PULL 09/10] integrator/cp: Implement CARDIN and WPROT signals
2015-03-11 14:18 [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell
` (7 preceding siblings ...)
2015-03-11 14:18 ` [Qemu-devel] [PULL 08/10] integrator/cp: Model CP control registers as sysbus device Peter Maydell
@ 2015-03-11 14:18 ` Peter Maydell
2015-03-11 14:18 ` [Qemu-devel] [PULL 10/10] bitops.h: sextract64() return type should be int64_t, not uint64_t Peter Maydell
2015-03-11 18:21 ` [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell
10 siblings, 0 replies; 32+ messages in thread
From: Peter Maydell @ 2015-03-11 14:18 UTC (permalink / raw)
To: qemu-devel
From: Jan Kiszka <jan.kiszka@siemens.com>
This allows to use the SD card emulation of the board: Forward the
signals from the pl181 top the CP control register emulation, report the
current state via CP_INTREG, deliver CARDIN IRQ to the secondary
interrupt controller and also support clearing that line via CP_INTREG.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Message-id: c55d9fb28d19ec83625cb0074b3b6f2e5958caf6.1426004843.git.jan.kiszka@siemens.com
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/integratorcp.c | 62 ++++++++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 56 insertions(+), 6 deletions(-)
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index 0dbda3a..cb609cd 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -416,18 +416,29 @@ typedef struct ICPCtrlRegsState {
/*< public >*/
MemoryRegion iomem;
+
+ qemu_irq mmc_irq;
+ uint32_t intreg_state;
} ICPCtrlRegsState;
+#define ICP_GPIO_MMC_WPROT "mmc-wprot"
+#define ICP_GPIO_MMC_CARDIN "mmc-cardin"
+
+#define ICP_INTREG_WPROT (1 << 0)
+#define ICP_INTREG_CARDIN (1 << 3)
+
static uint64_t icp_control_read(void *opaque, hwaddr offset,
unsigned size)
{
+ ICPCtrlRegsState *s = opaque;
+
switch (offset >> 2) {
case 0: /* CP_IDFIELD */
return 0x41034003;
case 1: /* CP_FLASHPROG */
return 0;
case 2: /* CP_INTREG */
- return 0;
+ return s->intreg_state;
case 3: /* CP_DECODE */
return 0x11;
default:
@@ -439,9 +450,14 @@ static uint64_t icp_control_read(void *opaque, hwaddr offset,
static void icp_control_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
+ ICPCtrlRegsState *s = opaque;
+
switch (offset >> 2) {
- case 1: /* CP_FLASHPROG */
case 2: /* CP_INTREG */
+ s->intreg_state &= ~(value & ICP_INTREG_CARDIN);
+ qemu_set_irq(s->mmc_irq, !!(s->intreg_state & ICP_INTREG_CARDIN));
+ break;
+ case 1: /* CP_FLASHPROG */
case 3: /* CP_DECODE */
/* Nothing interesting implemented yet. */
break;
@@ -456,14 +472,41 @@ static const MemoryRegionOps icp_control_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
+static void icp_control_mmc_wprot(void *opaque, int line, int level)
+{
+ ICPCtrlRegsState *s = opaque;
+
+ s->intreg_state &= ~ICP_INTREG_WPROT;
+ if (level) {
+ s->intreg_state |= ICP_INTREG_WPROT;
+ }
+}
+
+static void icp_control_mmc_cardin(void *opaque, int line, int level)
+{
+ ICPCtrlRegsState *s = opaque;
+
+ /* line is released by writing to CP_INTREG */
+ if (level) {
+ s->intreg_state |= ICP_INTREG_CARDIN;
+ qemu_set_irq(s->mmc_irq, 1);
+ }
+}
+
static void icp_control_init(Object *obj)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
ICPCtrlRegsState *s = ICP_CONTROL_REGS(obj);
+ DeviceState *dev = DEVICE(obj);
memory_region_init_io(&s->iomem, OBJECT(s), &icp_control_ops, s,
"icp_ctrl_regs", 0x00800000);
sysbus_init_mmio(sbd, &s->iomem);
+
+ qdev_init_gpio_in_named(dev, icp_control_mmc_wprot, ICP_GPIO_MMC_WPROT, 1);
+ qdev_init_gpio_in_named(dev, icp_control_mmc_cardin,
+ ICP_GPIO_MMC_CARDIN, 1);
+ sysbus_init_irq(sbd, &s->mmc_irq);
}
@@ -488,7 +531,7 @@ static void integratorcp_init(MachineState *machine)
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
qemu_irq pic[32];
- DeviceState *dev;
+ DeviceState *dev, *sic, *icp;
int i;
Error *err = NULL;
@@ -546,17 +589,24 @@ static void integratorcp_init(MachineState *machine)
for (i = 0; i < 32; i++) {
pic[i] = qdev_get_gpio_in(dev, i);
}
- sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]);
+ sic = sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]);
sysbus_create_varargs("integrator_pit", 0x13000000,
pic[5], pic[6], pic[7], NULL);
sysbus_create_simple("pl031", 0x15000000, pic[8]);
sysbus_create_simple("pl011", 0x16000000, pic[1]);
sysbus_create_simple("pl011", 0x17000000, pic[2]);
- sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000, NULL);
+ icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000,
+ qdev_get_gpio_in(sic, 3));
sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]);
sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]);
sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0);
- sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL);
+
+ dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL);
+ qdev_connect_gpio_out(dev, 0,
+ qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0));
+ qdev_connect_gpio_out(dev, 1,
+ qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0));
+
if (nd_table[0].used)
smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
--
1.9.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Qemu-devel] [PULL 10/10] bitops.h: sextract64() return type should be int64_t, not uint64_t
2015-03-11 14:18 [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell
` (8 preceding siblings ...)
2015-03-11 14:18 ` [Qemu-devel] [PULL 09/10] integrator/cp: Implement CARDIN and WPROT signals Peter Maydell
@ 2015-03-11 14:18 ` Peter Maydell
2015-03-11 18:21 ` [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell
10 siblings, 0 replies; 32+ messages in thread
From: Peter Maydell @ 2015-03-11 14:18 UTC (permalink / raw)
To: qemu-devel
The documentation for sextract64() claims that the return type is
an int64_t, but the code itself disagrees. Fix the return type to
conform to the documentation and to bring it into line with
sextract32(), which returns int32_t.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1423231328-15662-1-git-send-email-peter.maydell@linaro.org
---
include/qemu/bitops.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index 181bd46..90ca8df 100644
--- a/include/qemu/bitops.h
+++ b/include/qemu/bitops.h
@@ -354,7 +354,7 @@ static inline int32_t sextract32(uint32_t value, int start, int length)
* Returns: the sign extended value of the bit field extracted from the
* input value.
*/
-static inline uint64_t sextract64(uint64_t value, int start, int length)
+static inline int64_t sextract64(uint64_t value, int start, int length)
{
assert(start >= 0 && length > 0 && length <= 64 - start);
/* Note that this implementation relies on right shift of signed
--
1.9.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue
2015-03-11 14:18 [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell
` (9 preceding siblings ...)
2015-03-11 14:18 ` [Qemu-devel] [PULL 10/10] bitops.h: sextract64() return type should be int64_t, not uint64_t Peter Maydell
@ 2015-03-11 18:21 ` Peter Maydell
10 siblings, 0 replies; 32+ messages in thread
From: Peter Maydell @ 2015-03-11 18:21 UTC (permalink / raw)
To: QEMU Developers
On 11 March 2015 at 14:18, Peter Maydell <peter.maydell@linaro.org> wrote:
> target-arm queue: mostly bug fixes, but also the Netduino 2
> machine model. I'm letting that in (even though it's nearly
> hardfreeze) since a new board model isn't going to impact
> other existing uses, and the patches were posted well before
> softfreeze deadline.
Applied, thanks.
PS: if you see "unknown device" failures in make check, this
is a bug in our makefile/dependency generation stuff (currently
being worked on). The workaround is to
rm $BUILD_TREE/*/config-devices.mak
-- PMM
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue
2019-07-15 13:42 Peter Maydell
2019-07-15 14:18 ` Peter Maydell
2019-07-15 17:03 ` no-reply
@ 2019-07-16 8:55 ` no-reply
2 siblings, 0 replies; 32+ messages in thread
From: no-reply @ 2019-07-16 8:55 UTC (permalink / raw)
To: peter.maydell; +Cc: qemu-devel
Patchew URL: https://patchew.org/QEMU/20190715134211.23063-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [PULL 00/10] target-arm queue
Message-id: 20190715134211.23063-1-peter.maydell@linaro.org
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
From https://github.com/patchew-project/qemu
* [new tag] patchew/20190715134211.23063-1-peter.maydell@linaro.org -> patchew/20190715134211.23063-1-peter.maydell@linaro.org
Switched to a new branch 'test'
374fdb9 target/arm: NS BusFault on vector table fetch escalates to NS HardFault
a30b1da target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026
6d70517 pl031: Correctly migrate state when using -rtc clock=host
93d5845 hw/arm/virt: Fix non-secure flash mode
08594d9 hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO
d4bfee6 hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO
521dcfc hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]
28dc994 hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory
33d10d3 hw/ssi/xilinx_spips: Convert lqspi_read() to read_with_attrs
4ad540c target/arm: report ARMv8-A FP support for AArch32 -cpu max
=== OUTPUT BEGIN ===
1/10 Checking commit 4ad540cb003f (target/arm: report ARMv8-A FP support for AArch32 -cpu max)
2/10 Checking commit 33d10d39bd1e (hw/ssi/xilinx_spips: Convert lqspi_read() to read_with_attrs)
3/10 Checking commit 28dc994a8771 (hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory)
4/10 Checking commit 521dcfc62131 (hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[])
5/10 Checking commit d4bfee6403a6 (hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO)
6/10 Checking commit 08594d9831b4 (hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO)
7/10 Checking commit 93d58455baf6 (hw/arm/virt: Fix non-secure flash mode)
8/10 Checking commit 6d7051773f27 (pl031: Correctly migrate state when using -rtc clock=host)
ERROR: spaces required around that '*' (ctx:VxV)
#158: FILE: hw/timer/pl031.c:300:
+ .subsections = (const VMStateDescription*[]) {
^
total: 1 errors, 0 warnings, 146 lines checked
Patch 8/10 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/10 Checking commit a30b1dad815c (target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026)
10/10 Checking commit 374fdb936ee9 (target/arm: NS BusFault on vector table fetch escalates to NS HardFault)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190715134211.23063-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue
2019-07-15 13:42 Peter Maydell
2019-07-15 14:18 ` Peter Maydell
@ 2019-07-15 17:03 ` no-reply
2019-07-16 8:55 ` no-reply
2 siblings, 0 replies; 32+ messages in thread
From: no-reply @ 2019-07-15 17:03 UTC (permalink / raw)
To: peter.maydell; +Cc: qemu-devel
Patchew URL: https://patchew.org/QEMU/20190715134211.23063-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190715134211.23063-1-peter.maydell@linaro.org
Type: series
Subject: [Qemu-devel] [PULL 00/10] target-arm queue
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
From https://github.com/patchew-project/qemu
* [new tag] patchew/20190715134211.23063-1-peter.maydell@linaro.org -> patchew/20190715134211.23063-1-peter.maydell@linaro.org
Switched to a new branch 'test'
374fdb936e target/arm: NS BusFault on vector table fetch escalates to NS HardFault
a30b1dad81 target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026
6d7051773f pl031: Correctly migrate state when using -rtc clock=host
93d58455ba hw/arm/virt: Fix non-secure flash mode
08594d9831 hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO
d4bfee6403 hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO
521dcfc621 hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]
28dc994a87 hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory
33d10d39bd hw/ssi/xilinx_spips: Convert lqspi_read() to read_with_attrs
4ad540cb00 target/arm: report ARMv8-A FP support for AArch32 -cpu max
=== OUTPUT BEGIN ===
1/10 Checking commit 4ad540cb003f (target/arm: report ARMv8-A FP support for AArch32 -cpu max)
2/10 Checking commit 33d10d39bd1e (hw/ssi/xilinx_spips: Convert lqspi_read() to read_with_attrs)
3/10 Checking commit 28dc994a8771 (hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory)
4/10 Checking commit 521dcfc62131 (hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[])
5/10 Checking commit d4bfee6403a6 (hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO)
6/10 Checking commit 08594d9831b4 (hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO)
7/10 Checking commit 93d58455baf6 (hw/arm/virt: Fix non-secure flash mode)
8/10 Checking commit 6d7051773f27 (pl031: Correctly migrate state when using -rtc clock=host)
ERROR: spaces required around that '*' (ctx:VxV)
#158: FILE: hw/timer/pl031.c:300:
+ .subsections = (const VMStateDescription*[]) {
^
total: 1 errors, 0 warnings, 146 lines checked
Patch 8/10 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/10 Checking commit a30b1dad815c (target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026)
10/10 Checking commit 374fdb936ee9 (target/arm: NS BusFault on vector table fetch escalates to NS HardFault)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190715134211.23063-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue
2019-07-15 13:42 Peter Maydell
@ 2019-07-15 14:18 ` Peter Maydell
2019-07-15 17:03 ` no-reply
2019-07-16 8:55 ` no-reply
2 siblings, 0 replies; 32+ messages in thread
From: Peter Maydell @ 2019-07-15 14:18 UTC (permalink / raw)
To: QEMU Developers
On Mon, 15 Jul 2019 at 14:42, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> target-arm queue for rc1 -- these are all bug fixes.
>
> thanks
> -- PMM
>
> The following changes since commit b9404bf592e7ba74180e1a54ed7a266ec6ee67f2:
>
> Merge remote-tracking branch 'remotes/dgilbert/tags/pull-hmp-20190715' into staging (2019-07-15 12:22:07 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190715
>
> for you to fetch changes up to 51c9122e92b776a3f16af0b9282f1dc5012e2a19:
>
> target/arm: NS BusFault on vector table fetch escalates to NS HardFault (2019-07-15 14:17:04 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * report ARMv8-A FP support for AArch32 -cpu max
> * hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory
> * hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]
> * hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO
> * hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO
> * hw/arm/virt: Fix non-secure flash mode
> * pl031: Correctly migrate state when using -rtc clock=host
> * fix regression that meant arm926 and arm1026 lost VFP
> double-precision support
> * v8M: NS BusFault on vector table fetch escalates to NS HardFault
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/4.1
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Qemu-devel] [PULL 00/10] target-arm queue
@ 2019-07-15 13:42 Peter Maydell
2019-07-15 14:18 ` Peter Maydell
` (2 more replies)
0 siblings, 3 replies; 32+ messages in thread
From: Peter Maydell @ 2019-07-15 13:42 UTC (permalink / raw)
To: qemu-devel
target-arm queue for rc1 -- these are all bug fixes.
thanks
-- PMM
The following changes since commit b9404bf592e7ba74180e1a54ed7a266ec6ee67f2:
Merge remote-tracking branch 'remotes/dgilbert/tags/pull-hmp-20190715' into staging (2019-07-15 12:22:07 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190715
for you to fetch changes up to 51c9122e92b776a3f16af0b9282f1dc5012e2a19:
target/arm: NS BusFault on vector table fetch escalates to NS HardFault (2019-07-15 14:17:04 +0100)
----------------------------------------------------------------
target-arm queue:
* report ARMv8-A FP support for AArch32 -cpu max
* hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory
* hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]
* hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO
* hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO
* hw/arm/virt: Fix non-secure flash mode
* pl031: Correctly migrate state when using -rtc clock=host
* fix regression that meant arm926 and arm1026 lost VFP
double-precision support
* v8M: NS BusFault on vector table fetch escalates to NS HardFault
----------------------------------------------------------------
Alex Bennée (1):
target/arm: report ARMv8-A FP support for AArch32 -cpu max
David Engraf (1):
hw/arm/virt: Fix non-secure flash mode
Peter Maydell (3):
pl031: Correctly migrate state when using -rtc clock=host
target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026
target/arm: NS BusFault on vector table fetch escalates to NS HardFault
Philippe Mathieu-Daudé (5):
hw/ssi/xilinx_spips: Convert lqspi_read() to read_with_attrs
hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory
hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]
hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO
hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO
include/hw/timer/pl031.h | 2 ++
hw/arm/virt.c | 2 +-
hw/core/machine.c | 1 +
hw/display/xlnx_dp.c | 15 +++++---
hw/ssi/mss-spi.c | 8 ++++-
hw/ssi/xilinx_spips.c | 43 +++++++++++++++-------
hw/timer/pl031.c | 92 +++++++++++++++++++++++++++++++++++++++++++++---
target/arm/cpu.c | 16 +++++++++
target/arm/m_helper.c | 21 ++++++++---
9 files changed, 174 insertions(+), 26 deletions(-)
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue
2018-11-19 15:57 Peter Maydell
@ 2018-11-19 18:10 ` Peter Maydell
0 siblings, 0 replies; 32+ messages in thread
From: Peter Maydell @ 2018-11-19 18:10 UTC (permalink / raw)
To: QEMU Developers
On 19 November 2018 at 15:57, Peter Maydell <peter.maydell@linaro.org> wrote:
> Some Arm bugfixes for rc2...
>
> thanks
> -- PMM
>
> The following changes since commit e6ebbd46b6e539f3613136111977721d212c2812:
>
> Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-11-19 14:31:48 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181119
>
> for you to fetch changes up to a00d7f2048c2a1a6a4487ac195c804c78adcf60e:
>
> MAINTAINERS: list myself as maintainer for various Arm boards (2018-11-19 15:55:11 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * various MAINTAINERS file updates
> * hw/block/onenand: use qemu_log_mask() for reporting
> * hw/block/onenand: Fix off-by-one error allowing out-of-bounds read
> on the n800 and n810 machine models
> * target/arm: fix smc incorrectly trapping to EL3 when secure is off
> * hw/arm/stm32f205: Fix the UART and Timer region size
> * target/arm: read ID registers for KVM guests so they can be
> used to gate "is feature X present" checks
>
> ----------------------------------------------------------------
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Qemu-devel] [PULL 00/10] target-arm queue
@ 2018-11-19 15:57 Peter Maydell
2018-11-19 18:10 ` Peter Maydell
0 siblings, 1 reply; 32+ messages in thread
From: Peter Maydell @ 2018-11-19 15:57 UTC (permalink / raw)
To: qemu-devel
Some Arm bugfixes for rc2...
thanks
-- PMM
The following changes since commit e6ebbd46b6e539f3613136111977721d212c2812:
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-11-19 14:31:48 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181119
for you to fetch changes up to a00d7f2048c2a1a6a4487ac195c804c78adcf60e:
MAINTAINERS: list myself as maintainer for various Arm boards (2018-11-19 15:55:11 +0000)
----------------------------------------------------------------
target-arm queue:
* various MAINTAINERS file updates
* hw/block/onenand: use qemu_log_mask() for reporting
* hw/block/onenand: Fix off-by-one error allowing out-of-bounds read
on the n800 and n810 machine models
* target/arm: fix smc incorrectly trapping to EL3 when secure is off
* hw/arm/stm32f205: Fix the UART and Timer region size
* target/arm: read ID registers for KVM guests so they can be
used to gate "is feature X present" checks
----------------------------------------------------------------
Luc Michel (1):
target/arm: fix smc incorrectly trapping to EL3 when secure is off
Peter Maydell (3):
hw/block/onenand: Fix off-by-one error allowing out-of-bounds read
hw/block/onenand: use qemu_log_mask() for reporting
MAINTAINERS: list myself as maintainer for various Arm boards
Richard Henderson (4):
target/arm: Install ARMISARegisters from kvm host
target/arm: Fill in ARMISARegisters for kvm64
target/arm: Introduce read_sys_reg32 for kvm32
target/arm: Fill in ARMISARegisters for kvm32
Seth Kintigh (1):
hw/arm/stm32f205: Fix the UART and Timer region size
Thomas Huth (1):
MAINTAINERS: Add entries for missing ARM boards
target/arm/kvm_arm.h | 1 +
hw/block/onenand.c | 24 +++++-----
hw/char/stm32f2xx_usart.c | 2 +-
hw/timer/stm32f2xx_timer.c | 2 +-
target/arm/kvm.c | 1 +
target/arm/kvm32.c | 77 ++++++++++++++++++++------------
target/arm/kvm64.c | 90 +++++++++++++++++++++++++++++++++++++-
target/arm/op_helper.c | 54 +++++++++++++++++++----
MAINTAINERS | 106 +++++++++++++++++++++++++++++++++++++++------
9 files changed, 293 insertions(+), 64 deletions(-)
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue
2018-03-23 18:49 Peter Maydell
2018-03-23 21:45 ` no-reply
@ 2018-03-25 15:04 ` Peter Maydell
1 sibling, 0 replies; 32+ messages in thread
From: Peter Maydell @ 2018-03-25 15:04 UTC (permalink / raw)
To: QEMU Developers
On 23 March 2018 at 18:49, Peter Maydell <peter.maydell@linaro.org> wrote:
> Ten arm-related bug fixes for 2.12...
>
> thanks
> -- PMM
>
> The following changes since commit 4c2c1015905fa1d616750dfe024b4c0b35875950:
>
> Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20180323' into staging (2018-03-23 10:20:54 +0000)
>
> are available in the Git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180323
>
> for you to fetch changes up to 548f514cf89dd9ab39c0cb4c063097bccf141fdd:
>
> target/arm: Always set FAR to a known unknown value for debug exceptions (2018-03-23 18:26:46 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * arm/translate-a64: don't lose interrupts after unmasking via write to DAIF
> * sdhci: fix incorrect use of Error *
> * hw/intc/arm_gicv3: Fix secure-GIC NS ICC_PMR and ICC_RPR accesses
> * hw/arm/bcm2836: Use the Cortex-A7 instead of Cortex-A15
> * i.MX: Support serial RS-232 break properly
> * mach-virt: Set VM's SMBIOS system version to mc->name
> * target/arm: Honour MDCR_EL2.TDE when routing exceptions due to BKPT/BRK
> * target/arm: Factor out code to calculate FSR for debug exceptions
> * target/arm: Set FSR for BKPT, BRK when raising exception
> * target/arm: Always set FAR to a known unknown value for debug exceptions
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue
2018-03-23 18:49 Peter Maydell
@ 2018-03-23 21:45 ` no-reply
2018-03-25 15:04 ` Peter Maydell
1 sibling, 0 replies; 32+ messages in thread
From: no-reply @ 2018-03-23 21:45 UTC (permalink / raw)
To: peter.maydell; +Cc: famz, qemu-devel
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180323184958.14252-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/10] target-arm queue
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
e4250a6575 target/arm: Always set FAR to a known unknown value for debug exceptions
5f8ad1e5dc target/arm: Set FSR for BKPT, BRK when raising exception
1f8698e782 target/arm: Factor out code to calculate FSR for debug exceptions
01c3c783a2 target/arm: Honour MDCR_EL2.TDE when routing exceptions due to BKPT/BRK
6fdd8ed47e mach-virt: Set VM's SMBIOS system version to mc->name
4c27421e3d i.MX: Support serial RS-232 break properly
541bf9ad10 hw/arm/bcm2836: Use the Cortex-A7 instead of Cortex-A15
4ba4d6edd9 hw/intc/arm_gicv3: Fix secure-GIC NS ICC_PMR and ICC_RPR accesses
c5d1bc28c0 sdhci: fix incorrect use of Error *
c8c419d13c arm/translate-a64: treat DISAS_UPDATE as variant of DISAS_EXIT
=== OUTPUT BEGIN ===
Checking PATCH 1/10: arm/translate-a64: treat DISAS_UPDATE as variant of DISAS_EXIT...
Checking PATCH 2/10: sdhci: fix incorrect use of Error *...
Checking PATCH 3/10: hw/intc/arm_gicv3: Fix secure-GIC NS ICC_PMR and ICC_RPR accesses...
Checking PATCH 4/10: hw/arm/bcm2836: Use the Cortex-A7 instead of Cortex-A15...
Checking PATCH 5/10: i.MX: Support serial RS-232 break properly...
ERROR: spaces required around that '<<' (ctx:VxV)
#56: FILE: include/hw/char/imx_serial.h:29:
+#define URXD_FRMERR (1<<12) /* Character has frame error */
^
total: 1 errors, 0 warnings, 24 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 6/10: mach-virt: Set VM's SMBIOS system version to mc->name...
Checking PATCH 7/10: target/arm: Honour MDCR_EL2.TDE when routing exceptions due to BKPT/BRK...
Checking PATCH 8/10: target/arm: Factor out code to calculate FSR for debug exceptions...
Checking PATCH 9/10: target/arm: Set FSR for BKPT, BRK when raising exception...
Checking PATCH 10/10: target/arm: Always set FAR to a known unknown value for debug exceptions...
=== OUTPUT END ===
Test command exited with code: 1
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Qemu-devel] [PULL 00/10] target-arm queue
@ 2018-03-23 18:49 Peter Maydell
2018-03-23 21:45 ` no-reply
2018-03-25 15:04 ` Peter Maydell
0 siblings, 2 replies; 32+ messages in thread
From: Peter Maydell @ 2018-03-23 18:49 UTC (permalink / raw)
To: qemu-devel
Ten arm-related bug fixes for 2.12...
thanks
-- PMM
The following changes since commit 4c2c1015905fa1d616750dfe024b4c0b35875950:
Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20180323' into staging (2018-03-23 10:20:54 +0000)
are available in the Git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180323
for you to fetch changes up to 548f514cf89dd9ab39c0cb4c063097bccf141fdd:
target/arm: Always set FAR to a known unknown value for debug exceptions (2018-03-23 18:26:46 +0000)
----------------------------------------------------------------
target-arm queue:
* arm/translate-a64: don't lose interrupts after unmasking via write to DAIF
* sdhci: fix incorrect use of Error *
* hw/intc/arm_gicv3: Fix secure-GIC NS ICC_PMR and ICC_RPR accesses
* hw/arm/bcm2836: Use the Cortex-A7 instead of Cortex-A15
* i.MX: Support serial RS-232 break properly
* mach-virt: Set VM's SMBIOS system version to mc->name
* target/arm: Honour MDCR_EL2.TDE when routing exceptions due to BKPT/BRK
* target/arm: Factor out code to calculate FSR for debug exceptions
* target/arm: Set FSR for BKPT, BRK when raising exception
* target/arm: Always set FAR to a known unknown value for debug exceptions
----------------------------------------------------------------
Paolo Bonzini (1):
sdhci: fix incorrect use of Error *
Peter Maydell (6):
hw/intc/arm_gicv3: Fix secure-GIC NS ICC_PMR and ICC_RPR accesses
hw/arm/bcm2836: Use the Cortex-A7 instead of Cortex-A15
target/arm: Honour MDCR_EL2.TDE when routing exceptions due to BKPT/BRK
target/arm: Factor out code to calculate FSR for debug exceptions
target/arm: Set FSR for BKPT, BRK when raising exception
target/arm: Always set FAR to a known unknown value for debug exceptions
Trent Piepho (1):
i.MX: Support serial RS-232 break properly
Victor Kamensky (1):
arm/translate-a64: treat DISAS_UPDATE as variant of DISAS_EXIT
Wei Huang (1):
mach-virt: Set VM's SMBIOS system version to mc->name
include/hw/arm/virt.h | 1 +
include/hw/char/imx_serial.h | 1 +
target/arm/helper.h | 1 +
target/arm/internals.h | 25 +++++++++++++++++++++++++
hw/arm/bcm2836.c | 2 +-
hw/arm/raspi.c | 2 +-
hw/arm/virt.c | 8 +++++++-
hw/char/imx_serial.c | 5 ++++-
hw/intc/arm_gicv3_cpuif.c | 6 +++---
hw/sd/sdhci.c | 4 ++--
target/arm/helper.c | 1 -
target/arm/op_helper.c | 33 ++++++++++++++++++++++-----------
target/arm/translate-a64.c | 21 ++++++++++++++++-----
target/arm/translate.c | 19 ++++++++++++++-----
14 files changed, 98 insertions(+), 31 deletions(-)
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue
2014-05-04 19:45 ` Richard W.M. Jones
@ 2014-05-04 19:55 ` Peter Maydell
0 siblings, 0 replies; 32+ messages in thread
From: Peter Maydell @ 2014-05-04 19:55 UTC (permalink / raw)
To: Richard W.M. Jones; +Cc: QEMU Developers, Anthony Liguori
On 4 May 2014 20:45, Richard W.M. Jones <rjones@redhat.com> wrote:
> On Sun, May 04, 2014 at 08:36:20PM +0100, Peter Maydell wrote:
>> OK, so you have a kernel (possibly just kernel config) problem
>> here -- this means QEMU got EPERM trying to open /dev/kvm.
>
> Yes for some reason it was 0600. I set it to 0666.
>
>> This isn't going to work for aarch64 at the moment because:
>> * KVM aarch64 currently requires '-cpu host'
>
> OK -- I will play with libguestfs to make sure it passes this flag,
> and try again.
It should in theory be possible to get -cpu cortex-a57 to
work (though I haven't tried it so it's likely missing something
trivial); however that will only work if your host CPU is
actually a Cortex-A57. For any other host you'll need
-cpu host.
> Currently waiting for the host (which has panicked
> again) to be rebooted manually.
If your host has panicked that's a kernel bug :-) (or possibly
a hardware bug if you're unlucky). If it does so reproducibly
when you prod it with QEMU then you should probably retest
with a recent kernel and report it to the kvm-arm mailing list.
thanks
-- PMM
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue
2014-05-04 19:36 ` Peter Maydell
@ 2014-05-04 19:45 ` Richard W.M. Jones
2014-05-04 19:55 ` Peter Maydell
0 siblings, 1 reply; 32+ messages in thread
From: Richard W.M. Jones @ 2014-05-04 19:45 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers, Anthony Liguori
On Sun, May 04, 2014 at 08:36:20PM +0100, Peter Maydell wrote:
> OK, so you have a kernel (possibly just kernel config) problem
> here -- this means QEMU got EPERM trying to open /dev/kvm.
Yes for some reason it was 0600. I set it to 0666.
> This isn't going to work for aarch64 at the moment because:
> * KVM aarch64 currently requires '-cpu host'
OK -- I will play with libguestfs to make sure it passes this flag,
and try again. Currently waiting for the host (which has panicked
again) to be rebooted manually.
Thanks again,
Rich.
--
Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones
Read my programming and virtualization blog: http://rwmj.wordpress.com
virt-df lists disk usage of guests without needing to install any
software inside the virtual machine. Supports Linux and Windows.
http://people.redhat.com/~rjones/virt-df/
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue
2014-05-04 18:58 ` Richard W.M. Jones
@ 2014-05-04 19:36 ` Peter Maydell
2014-05-04 19:45 ` Richard W.M. Jones
0 siblings, 1 reply; 32+ messages in thread
From: Peter Maydell @ 2014-05-04 19:36 UTC (permalink / raw)
To: Richard W.M. Jones; +Cc: QEMU Developers, Anthony Liguori
On 4 May 2014 19:58, Richard W.M. Jones <rjones@redhat.com> wrote:
> On Sun, May 04, 2014 at 07:48:38PM +0100, Peter Maydell wrote:
>> On 4 May 2014 19:30, Richard W.M. Jones <rjones@redhat.com> wrote:
>> > I have real aarch64 hardware, and I'm trying to find a version of
>> > qemu-system-aarch64 which will boot a KVM guest in some form.
>> >
>> > Upstream qemu fails with a bizarre thread-local storage problem (yes,
>> > I've patched glibc to fix the makecontext problem).
>> >
>> > Is there a qemu tree I should be looking at?
>>
>> Upstream is it. I haven't been testing it for a while though; it's possible
>> it bitrotted while I wasn't looking.
>
> OK, it might be a kernel problem then.
>
> This was the issue I was having before:
>
> /home/rjones/d/qemu/aarch64-softmmu/qemu-system-aarch64 \
> -global virtio-blk-device.scsi=off \
> -nodefconfig \
> -enable-fips \
> -nodefaults \
> -display none \
> -M virt \
> -machine accel=kvm:tcg \
> -m 500 \
> -no-reboot \
> -rtc driftfix=slew \
> -global kvm-pit.lost_tick_policy=discard \
> -kernel /home/rjones/d/libguestfs/tmp/.guestfs-1000/appliance.d/kernel \
> -initrd /home/rjones/d/libguestfs/tmp/.guestfs-1000/appliance.d/initrd \
> -device virtio-scsi-device,id=scsi \
> -drive file=/home/rjones/d/libguestfs/tmp/libguestfsHRi4Tt/scratch.1,cache=unsafe,format=raw,id=hd0,if=none \
> -device scsi-hd,drive=hd0 \
> -drive file=/home/rjones/d/libguestfs/tmp/.guestfs-1000/appliance.d/root,snapshot=on,id=appliance,cache=unsafe,if=none \
> -device scsi-hd,drive=appliance \
> -device virtio-serial-device \
> -serial stdio \
> -chardev socket,path=/home/rjones/d/libguestfs/tmp/libguestfsHRi4Tt/guestfsd.sock,id=channel0 \
> -device virtserialport,chardev=channel0,name=org.libguestfs.channel.0 \
> -append 'panic=1 console=ttyS0 udevtimeout=600 no_timer_check acpi=off printk.time=1 cgroup_disable=memory root=/dev/sdb selinux=0 guestfs_verbose=1 TERM=screen'
> Could not access KVM kernel module: Permission denied
> failed to initialize KVM: Permission denied
> Back to tcg accelerator.
OK, so you have a kernel (possibly just kernel config) problem
here -- this means QEMU got EPERM trying to open /dev/kvm.
This isn't going to work for aarch64 at the moment because:
* KVM aarch64 currently requires '-cpu host'
* '-cpu host' is a KVM only thing that won't work with TCG
If you don't enable KVM we don't put 'host' in the CPU list
so usually the TCG code can't see it -- however "use KVM
but have the init fail" is a path I hadn't considered for getting
into TCG with -cpu host.
Does this happen if you start with accel=tcg so we're using
TCG all the way through?
You can also ignore all this in favour of just figuring out why
your kernel didn't let us open /dev/kvm...
PS: I didn't see a "-cpu something" in your command line;
I forget what the default is but it's probably not what you want.
> libguestfs: error: appliance closed the connection unexpectedly, see earlier error messages
> libguestfs: child_cleanup: 0x3b5a1770: child process died
> libguestfs: sending SIGTERM to process 12438
> libguestfs: error: /home/rjones/d/qemu/aarch64-softmmu/qemu-system-aarch64 killed by signal 11 (Segmentation fault), see debug messages above
>
> The stack trace in qemu when the segfault occurs is:
>
> Program terminated with signal SIGSEGV, Segmentation fault.
> #0 0x000002aae2f17394 in cpu_arm_exec (env=0x3ff8401eed0,
> env@entry=0x2ab1c978440) at /home/rjones/d/qemu/cpu-exec.c:241
> 241 current_cpu = cpu;
>
> (gdb) print tls__current_cpu
> Cannot find thread-local storage for LWP 12922, executable file /home/rjones/d/qemu/aarch64-softmmu/qemu-system-aarch64:
> TLS not supported on this target
>
> ... and ^^^ that's the part that makes no sense to me. TLS must
> surely be supported, so there must be something odd about the
> compile-time environment.
I think that message is gdb saying that it doesn't support TLS,
not that the target architecture doesn't support TLS. How ancient
is your gdb? Google suggests that TLS support went into the
aarch64 target somewhat after the initial architecture support
(though still a year or so ago, so I would have expected it to get in...)
thanks
-- PMM
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue
2014-05-04 18:48 ` Peter Maydell
2014-05-04 18:58 ` Richard W.M. Jones
@ 2014-05-04 19:29 ` Richard W.M. Jones
1 sibling, 0 replies; 32+ messages in thread
From: Richard W.M. Jones @ 2014-05-04 19:29 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers, Anthony Liguori
I think this problem comes from my environment adding -fPIE.
In any case, without that flag it doesn't crash in qemu (it
kernel panics instead ..)
Rich.
--
Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones
Read my programming and virtualization blog: http://rwmj.wordpress.com
libguestfs lets you edit virtual machines. Supports shell scripting,
bindings from many languages. http://libguestfs.org
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue
2014-05-04 18:48 ` Peter Maydell
@ 2014-05-04 18:58 ` Richard W.M. Jones
2014-05-04 19:36 ` Peter Maydell
2014-05-04 19:29 ` Richard W.M. Jones
1 sibling, 1 reply; 32+ messages in thread
From: Richard W.M. Jones @ 2014-05-04 18:58 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers, Anthony Liguori
On Sun, May 04, 2014 at 07:48:38PM +0100, Peter Maydell wrote:
> On 4 May 2014 19:30, Richard W.M. Jones <rjones@redhat.com> wrote:
> > I have real aarch64 hardware, and I'm trying to find a version of
> > qemu-system-aarch64 which will boot a KVM guest in some form.
> >
> > Upstream qemu fails with a bizarre thread-local storage problem (yes,
> > I've patched glibc to fix the makecontext problem).
> >
> > Is there a qemu tree I should be looking at?
>
> Upstream is it. I haven't been testing it for a while though; it's possible
> it bitrotted while I wasn't looking.
OK, it might be a kernel problem then.
This was the issue I was having before:
/home/rjones/d/qemu/aarch64-softmmu/qemu-system-aarch64 \
-global virtio-blk-device.scsi=off \
-nodefconfig \
-enable-fips \
-nodefaults \
-display none \
-M virt \
-machine accel=kvm:tcg \
-m 500 \
-no-reboot \
-rtc driftfix=slew \
-global kvm-pit.lost_tick_policy=discard \
-kernel /home/rjones/d/libguestfs/tmp/.guestfs-1000/appliance.d/kernel \
-initrd /home/rjones/d/libguestfs/tmp/.guestfs-1000/appliance.d/initrd \
-device virtio-scsi-device,id=scsi \
-drive file=/home/rjones/d/libguestfs/tmp/libguestfsHRi4Tt/scratch.1,cache=unsafe,format=raw,id=hd0,if=none \
-device scsi-hd,drive=hd0 \
-drive file=/home/rjones/d/libguestfs/tmp/.guestfs-1000/appliance.d/root,snapshot=on,id=appliance,cache=unsafe,if=none \
-device scsi-hd,drive=appliance \
-device virtio-serial-device \
-serial stdio \
-chardev socket,path=/home/rjones/d/libguestfs/tmp/libguestfsHRi4Tt/guestfsd.sock,id=channel0 \
-device virtserialport,chardev=channel0,name=org.libguestfs.channel.0 \
-append 'panic=1 console=ttyS0 udevtimeout=600 no_timer_check acpi=off printk.time=1 cgroup_disable=memory root=/dev/sdb selinux=0 guestfs_verbose=1 TERM=screen'
Could not access KVM kernel module: Permission denied
failed to initialize KVM: Permission denied
Back to tcg accelerator.
libguestfs: error: appliance closed the connection unexpectedly, see earlier error messages
libguestfs: child_cleanup: 0x3b5a1770: child process died
libguestfs: sending SIGTERM to process 12438
libguestfs: error: /home/rjones/d/qemu/aarch64-softmmu/qemu-system-aarch64 killed by signal 11 (Segmentation fault), see debug messages above
The stack trace in qemu when the segfault occurs is:
Program terminated with signal SIGSEGV, Segmentation fault.
#0 0x000002aae2f17394 in cpu_arm_exec (env=0x3ff8401eed0,
env@entry=0x2ab1c978440) at /home/rjones/d/qemu/cpu-exec.c:241
241 current_cpu = cpu;
(gdb) print tls__current_cpu
Cannot find thread-local storage for LWP 12922, executable file /home/rjones/d/qemu/aarch64-softmmu/qemu-system-aarch64:
TLS not supported on this target
... and ^^^ that's the part that makes no sense to me. TLS must
surely be supported, so there must be something odd about the
compile-time environment.
Linux ***.redhat.com 3.13.0-0.rc7.31.***.aarch64.debug #1 SMP Fri May 2 16:55:22 EDT 2014 aarch64 aarch64 aarch64 GNU/Linux
glibc-2.19.90-11.fc21.aarch64
gcc-4.9.0-1.fc21.aarch64
Rich.
--
Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones
Read my programming and virtualization blog: http://rwmj.wordpress.com
virt-df lists disk usage of guests without needing to install any
software inside the virtual machine. Supports Linux and Windows.
http://people.redhat.com/~rjones/virt-df/
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue
2014-05-04 18:30 ` Richard W.M. Jones
@ 2014-05-04 18:48 ` Peter Maydell
2014-05-04 18:58 ` Richard W.M. Jones
2014-05-04 19:29 ` Richard W.M. Jones
0 siblings, 2 replies; 32+ messages in thread
From: Peter Maydell @ 2014-05-04 18:48 UTC (permalink / raw)
To: Richard W.M. Jones; +Cc: QEMU Developers, Anthony Liguori
On 4 May 2014 19:30, Richard W.M. Jones <rjones@redhat.com> wrote:
> I have real aarch64 hardware, and I'm trying to find a version of
> qemu-system-aarch64 which will boot a KVM guest in some form.
>
> Upstream qemu fails with a bizarre thread-local storage problem (yes,
> I've patched glibc to fix the makecontext problem).
>
> Is there a qemu tree I should be looking at?
Upstream is it. I haven't been testing it for a while though; it's possible
it bitrotted while I wasn't looking.
thanks
-- PMM
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue
2014-05-01 14:54 Peter Maydell
2014-05-02 11:11 ` Peter Maydell
@ 2014-05-04 18:30 ` Richard W.M. Jones
2014-05-04 18:48 ` Peter Maydell
1 sibling, 1 reply; 32+ messages in thread
From: Richard W.M. Jones @ 2014-05-04 18:30 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, Anthony Liguori
On Thu, May 01, 2014 at 03:54:57PM +0100, Peter Maydell wrote:
> Nothing earthshattering here, but it does have the patch which
> actually lets us boot an emulated AArch64 CPU on a board...
Hi Peter,
I have real aarch64 hardware, and I'm trying to find a version of
qemu-system-aarch64 which will boot a KVM guest in some form.
Upstream qemu fails with a bizarre thread-local storage problem (yes,
I've patched glibc to fix the makecontext problem).
Is there a qemu tree I should be looking at?
Rich.
--
Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones
Read my programming and virtualization blog: http://rwmj.wordpress.com
virt-p2v converts physical machines to virtual machines. Boot with a
live CD or over the network (PXE) and turn machines into KVM guests.
http://libguestfs.org/virt-v2v
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue
2014-05-01 14:54 Peter Maydell
@ 2014-05-02 11:11 ` Peter Maydell
2014-05-04 18:30 ` Richard W.M. Jones
1 sibling, 0 replies; 32+ messages in thread
From: Peter Maydell @ 2014-05-02 11:11 UTC (permalink / raw)
To: Anthony Liguori; +Cc: QEMU Developers
On 1 May 2014 15:54, Peter Maydell <peter.maydell@linaro.org> wrote:
> Nothing earthshattering here, but it does have the patch which
> actually lets us boot an emulated AArch64 CPU on a board...
>
> thanks
> -- PMM
>
> The following changes since commit 051b9980b99dbfba22ea5f79bd3708d513ae121d:
>
> Merge remote-tracking branch 'remotes/kraxel/tags/pull-gtk-6' into staging (2014-05-01 14:17:33 +0100)
>
> are available in the git repository at:
>
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20140501
>
> for you to fetch changes up to f42c5c8ec8aa0e15583487ffee62964830751623:
>
> hw/arm/virt: Add support for Cortex-A57 (2014-05-01 15:25:52 +0100)
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Qemu-devel] [PULL 00/10] target-arm queue
@ 2014-05-01 14:54 Peter Maydell
2014-05-02 11:11 ` Peter Maydell
2014-05-04 18:30 ` Richard W.M. Jones
0 siblings, 2 replies; 32+ messages in thread
From: Peter Maydell @ 2014-05-01 14:54 UTC (permalink / raw)
To: Anthony Liguori; +Cc: qemu-devel
Nothing earthshattering here, but it does have the patch which
actually lets us boot an emulated AArch64 CPU on a board...
thanks
-- PMM
The following changes since commit 051b9980b99dbfba22ea5f79bd3708d513ae121d:
Merge remote-tracking branch 'remotes/kraxel/tags/pull-gtk-6' into staging (2014-05-01 14:17:33 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20140501
for you to fetch changes up to f42c5c8ec8aa0e15583487ffee62964830751623:
hw/arm/virt: Add support for Cortex-A57 (2014-05-01 15:25:52 +0100)
----------------------------------------------------------------
target-arm queue:
* implement XScale cache lockdown cp15 ops
* fix v7M CPUID base register
* implement WFE and YIELD as yields for A64
* fix A64 "BLR LR"
* support Cortex-A57 in virt machine model
* a few other minor AArch64 bugfixes
----------------------------------------------------------------
Edgar E. Iglesias (4):
target-arm: Make vbar_write 64bit friendly on 32bit hosts
target-arm: A64: Handle blr lr
target-arm: A64: Fix a typo when declaring TLBI ops
target-arm: Correct a comment refering to EL0
Peter Maydell (4):
target-arm: Implement XScale cache lockdown operations as NOPs
hw/arm/virt: Create the GIC ourselves rather than (ab)using a15mpcore_priv
hw/arm/virt: Put GIC register banks on 64K boundaries
hw/arm/virt: Add support for Cortex-A57
Rabin Vincent (1):
armv7m_nvic: fix CPUID Base Register
Rob Herring (1):
target-arm: implement WFE/YIELD as a yield for AArch64
hw/arm/virt.c | 93 ++++++++++++++++++++++++++++++----------------
hw/intc/armv7m_nvic.c | 2 +-
target-arm/helper.c | 41 +++++++++++++-------
target-arm/op_helper.c | 2 +-
target-arm/translate-a64.c | 9 ++++-
5 files changed, 99 insertions(+), 48 deletions(-)
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Qemu-devel] [PULL 00/10] target-arm queue
2011-12-13 18:30 Peter Maydell
@ 2011-12-14 20:41 ` andrzej zaborowski
0 siblings, 0 replies; 32+ messages in thread
From: andrzej zaborowski @ 2011-12-14 20:41 UTC (permalink / raw)
To: Peter Maydell; +Cc: Anthony Liguori, Paul Brook, qemu-devel
On 13 December 2011 19:30, Peter Maydell <peter.maydell@linaro.org> wrote:
> Current target-arm pending patches; mostly these are Andreas'
> inference series, plus one from Jean-Christophe that's been
> waiting since before the 1.0 release.
>
> Please pull.
Thanks, pulled (and pushed)
Cheers
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Qemu-devel] [PULL 00/10] target-arm queue
@ 2011-12-13 18:30 Peter Maydell
2011-12-14 20:41 ` andrzej zaborowski
0 siblings, 1 reply; 32+ messages in thread
From: Peter Maydell @ 2011-12-13 18:30 UTC (permalink / raw)
To: Anthony Liguori; +Cc: Paul Brook, qemu-devel
Current target-arm pending patches; mostly these are Andreas'
inference series, plus one from Jean-Christophe that's been
waiting since before the 1.0 release.
Please pull.
-- PMM
The following changes since commit da5361cc685c004d8bb4e7c5e7b3a52c7aca2c56:
ccid: make threads joinable (2011-12-12 17:06:22 -0600)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream
Andreas Färber (9):
target-arm: Infer ARMv4T feature from ARMv5
target-arm: Infer ARMv5 feature from ARMv6
target-arm: Infer ARMv6 feature from v6K
target-arm: Infer ARMv6(K) feature from ARMv7
target-arm: Infer AUXCR feature from ARMv6
target-arm: Infer Thumb2 feature from ARMv7
target-arm: Infer Thumb division feature from M profile
target-arm: Infer VFP feature from VFPv3
target-arm: Infer VFPv3 feature from VFPv4
Jean-Christophe DUBOIS (1):
arm: Fix CP15 FSR (C5) domain setting
target-arm/helper.c | 95 ++++++++++++++++++++++----------------------------
1 files changed, 42 insertions(+), 53 deletions(-)
^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2019-07-16 8:56 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-03-11 14:18 [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell
2015-03-11 14:18 ` [Qemu-devel] [PULL 01/10] hw/arm/virt: fix cmdline parsing bug with CPU options and smp > 1 Peter Maydell
2015-03-11 14:18 ` [Qemu-devel] [PULL 02/10] stm32f2xx_timer: Add the stm32f2xx Timer Peter Maydell
2015-03-11 14:18 ` [Qemu-devel] [PULL 03/10] stm32f2xx_USART: Add the stm32f2xx USART Controller Peter Maydell
2015-03-11 14:18 ` [Qemu-devel] [PULL 04/10] stm32f2xx_SYSCFG: Add the stm32f2xx SYSCFG Peter Maydell
2015-03-11 14:18 ` [Qemu-devel] [PULL 05/10] stm32f205: Add the stm32f205 SoC Peter Maydell
2015-03-11 14:18 ` [Qemu-devel] [PULL 06/10] netduino2: Add the Netduino 2 Machine Peter Maydell
2015-03-11 14:18 ` [Qemu-devel] [PULL 07/10] target-arm: Add missing compatible property to A57 Peter Maydell
2015-03-11 14:18 ` [Qemu-devel] [PULL 08/10] integrator/cp: Model CP control registers as sysbus device Peter Maydell
2015-03-11 14:18 ` [Qemu-devel] [PULL 09/10] integrator/cp: Implement CARDIN and WPROT signals Peter Maydell
2015-03-11 14:18 ` [Qemu-devel] [PULL 10/10] bitops.h: sextract64() return type should be int64_t, not uint64_t Peter Maydell
2015-03-11 18:21 ` [Qemu-devel] [PULL 00/10] target-arm queue Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2019-07-15 13:42 Peter Maydell
2019-07-15 14:18 ` Peter Maydell
2019-07-15 17:03 ` no-reply
2019-07-16 8:55 ` no-reply
2018-11-19 15:57 Peter Maydell
2018-11-19 18:10 ` Peter Maydell
2018-03-23 18:49 Peter Maydell
2018-03-23 21:45 ` no-reply
2018-03-25 15:04 ` Peter Maydell
2014-05-01 14:54 Peter Maydell
2014-05-02 11:11 ` Peter Maydell
2014-05-04 18:30 ` Richard W.M. Jones
2014-05-04 18:48 ` Peter Maydell
2014-05-04 18:58 ` Richard W.M. Jones
2014-05-04 19:36 ` Peter Maydell
2014-05-04 19:45 ` Richard W.M. Jones
2014-05-04 19:55 ` Peter Maydell
2014-05-04 19:29 ` Richard W.M. Jones
2011-12-13 18:30 Peter Maydell
2011-12-14 20:41 ` andrzej zaborowski
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