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From: Peter Maydell <peter.maydell@linaro.org>
To: Peter Crosthwaite <crosthwaitepeter@gmail.com>
Cc: "Edgar Iglesias" <edgar.iglesias@xilinx.com>,
	"Edgar Iglesias" <edgar.iglesias@gmail.com>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"Andreas Färber" <afaerber@suse.de>,
	"Alistair Francis" <alistair.francis@xilinx.com>
Subject: Re: [Qemu-devel] [PATCH v1 00/15] data-driven device registers
Date: Tue, 15 Dec 2015 21:56:12 +0000	[thread overview]
Message-ID: <CAFEAcA98ojuuSHW5Y=eDEK0Rxfk7-6teDW1mrke3SpsuQXEZfQ@mail.gmail.com> (raw)
In-Reply-To: <CAPokK=p4BLhsPi1vb_OxAmPQz4r1EL9G1V3kgqx5t-ZKRsfOZw@mail.gmail.com>

On 15 December 2015 at 20:52, Peter Crosthwaite
<crosthwaitepeter@gmail.com> wrote:
> It needs to exist before it can be used so there is a bit of a chicken
> and egg problem there.

Right, but the hope would be that there's somebody who cares
about device models who thinks it's worthwhile... if we really
do only have three people who write devices then that's a bit sad.

> It is originally my code and Alistair has taken
> ownership of it so that excludes the both of us. Aside from yourself,
> there aren't too many new device-model authors out there who are
> active review. Do you have a nominee?

For instance, do any of the MIPS, PPC or SPARC maintainers see
it as useful for their devices?

> I'll throw a new argument into the mix that is closer to home for
> yourself, it has a lot in common with the ARM CP API. If we converted
> the ARM CP API to be data driven rather than code driven (which we
> have), why are MMIO devices so different? CP accesses can be
> side-effectless or require side-effect causing functions, and 99% of
> sysbus devices fit this description. Ideally, I'd like to mass-covert
> CP API to use something like this for one API to rule them all. If I
> instead morphed the CP API to a generic feature in hw/core, extended
> with the features of this patch set, would that work better for you?
> Then both devices and custom register APIs (like CP) can be
> standardised. Note that this is already two layered. The concept of
> the register API which defines collections of registers is separate
> from sysbus.

The coprocessor APIs are data driven because we had the previous
lots-of-switch-statements approach and it was terrible to
maintain. On the other hand I look at the average device
(say hw/misc/a9scu.c or hw/misc/arm_sysctl.c) and it doesn't
really seem that hard to deal with (in particular you only
have one level of switching, on the register address, rather
than four levels with opc1/opc2/crn/crm, and your average
device has tens of registers rather than hundreds).

Basically, the cp API change was a bit of an upheaval but
clearly worthwhile because we were feeling the pain of not
having it. I'm not convinced we're feeling that much pain from
our current approach to device registers, and I'm definitely
not convinced that we'd make a wholesale conversion to use
this new API the way we did with the cp API.

As I say, I don't fundamentally object to this, but I'd be
happier if you convinced some other developer of the utility...

thanks
-- PMM

  reply	other threads:[~2015-12-15 21:56 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-29 20:24 [Qemu-devel] [PATCH v1 00/15] data-driven device registers Alistair Francis
2015-07-29 20:24 ` [Qemu-devel] [PATCH v1 01/15] register: Add Register API Alistair Francis
2015-07-29 20:24 ` [Qemu-devel] [PATCH v1 02/15] register: Add Memory API glue Alistair Francis
2015-07-29 20:24 ` [Qemu-devel] [PATCH v1 03/15] register: Add support for decoding information Alistair Francis
2015-07-29 20:24 ` [Qemu-devel] [PATCH v1 04/15] register: Define REG and FIELD macros Alistair Francis
2015-07-29 20:24 ` [Qemu-devel] [PATCH v1 05/15] register: QOMify Alistair Francis
2015-07-29 20:24 ` [Qemu-devel] [PATCH v1 06/15] register: Add block initialise helper Alistair Francis
2015-07-29 20:24 ` [Qemu-devel] [PATCH v1 07/15] bitops: Add ONES macro Alistair Francis
2015-07-29 20:24 ` [Qemu-devel] [PATCH v1 08/15] dma: Add Xilinx Zynq devcfg device model Alistair Francis
2015-07-29 20:24 ` [Qemu-devel] [PATCH v1 09/15] xilinx_zynq: add devcfg to machine model Alistair Francis
2015-07-29 20:24 ` [Qemu-devel] [PATCH v1 10/15] qdev: Define qdev_get_gpio_out Alistair Francis
2015-07-29 20:25 ` [Qemu-devel] [PATCH v1 11/15] qdev: Add qdev_pass_all_gpios API Alistair Francis
2015-07-29 20:25 ` [Qemu-devel] [PATCH v1 12/15] irq: Add opaque setter routine Alistair Francis
2015-07-29 20:25 ` [Qemu-devel] [PATCH v1 13/15] register: Add GPIO API Alistair Francis
2015-07-29 20:25 ` [Qemu-devel] [PATCH v1 14/15] misc: Introduce ZynqMP IOU SLCR Alistair Francis
2015-07-29 20:25 ` [Qemu-devel] [PATCH v1 15/15] xlnx-zynqmp: Connect the " Alistair Francis
2015-08-27 21:47 ` [Qemu-devel] [PATCH v1 00/15] data-driven device registers Alistair Francis
2015-10-14 18:42   ` Alistair Francis
2015-10-30  6:52     ` Peter Crosthwaite
2015-10-30  8:06       ` Peter Maydell
2015-12-15 19:46         ` Peter Maydell
2015-12-15 20:52           ` Peter Crosthwaite
2015-12-15 21:56             ` Peter Maydell [this message]
2015-12-16 16:33               ` Alistair Francis
2016-01-08  0:39                 ` Alistair Francis
2016-01-08 10:40                   ` Peter Maydell
2016-01-08 11:05                     ` Edgar E. Iglesias
2016-01-19 19:51                       ` Alistair Francis
2016-01-19 21:35                         ` Edgar E. Iglesias
2016-01-28 16:31                     ` Frederic Konrad
2016-01-28 16:34                       ` Peter Maydell
2016-01-30  0:56                         ` Alistair Francis

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