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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Qemu-block , QEMU Developers , Aleksandar Markovic , Stafford Horne , John Snow , Aleksandar Rikalo , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, 12 May 2020 at 08:48, Philippe Mathieu-Daud=C3=A9 = wrote: > > Switch to using the qdev gpio API which is preferred over > qemu_allocate_irqs(). One step to eventually deprecate and > remove qemu_allocate_irqs() one day. > diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c > index 796730b11d..91788c51a9 100644 > --- a/hw/mips/mips_int.c > +++ b/hw/mips/mips_int.c > @@ -74,14 +74,12 @@ static void cpu_mips_irq_request(void *opaque, int ir= q, int level) > void cpu_mips_irq_init_cpu(MIPSCPU *cpu) > { > CPUMIPSState *env =3D &cpu->env; > - qemu_irq *qi; > int i; > > - qi =3D qemu_allocate_irqs(cpu_mips_irq_request, cpu, 8); > + qdev_init_gpio_in(DEVICE(cpu), cpu_mips_irq_request, 8); > for (i =3D 0; i < 8; i++) { > - env->irq[i] =3D qi[i]; > + env->irq[i] =3D qdev_get_gpio_in(DEVICE(cpu), i); > } > - g_free(qi); > } Similar comments as with the openrisc patch apply here: * ideally this code should be in target/mips/, not in hw/mips * board code should call qdev_get_gpio_in() to get the IRQ line, rather than fishing env->irq[] out of the CPU object directly This is a bit more complicated than with openrisc, because there's more than just a single board model, and not all MIPS boards call cpu_mips_irq_init_cpu() so figuring out whether MIPS CPUs should always provide inbound CPU lines, or only those with some particular feature, or something else, would need some investigation or MIPS knowledge. But this is an OK first step anyway, so Reviewed-by: Peter Maydell thanks -- PMM