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Thu, 08 Jul 2021 02:51:23 -0700 (PDT) MIME-Version: 1.0 References: <20210706134457.81059-1-hnick@vmware.com> In-Reply-To: <20210706134457.81059-1-hnick@vmware.com> From: Peter Maydell Date: Thu, 8 Jul 2021 10:50:45 +0100 Message-ID: Subject: Re: [PATCH v2] target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint To: Nick Hudson Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:ARM TCG CPUs" , Mohannad Ismail , "open list:All patches CC here" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, 6 Jul 2021 at 14:45, wrote: > > Signed-off-by: Nick Hudson > --- > target/arm/helper.c | 16 +++++++++++++--- > 1 file changed, 13 insertions(+), 3 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index a66c1f0b9e..910ace4274 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6326,11 +6326,21 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { > .access = PL1_RW, .accessfn = access_tda, > .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), > .resetvalue = 0 }, > - /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. > + /* > + * MDCCSR_EL0[30:29] map to EDSCR[30:29]. Simply RAZ as the external > + * Debug Communication Channel is not implemented. > + */ > + { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64, > + .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0, > + .access = PL0_R, .accessfn = access_tda, > + .type = ARM_CP_CONST, .resetvalue = 0 }, > + /* > + * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as > + * it is unlikely a guest will care. > * We don't implement the configurable EL0 access. > */ > - { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH, > - .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, > + { .name = "DBGDSCRint", .state = ARM_CP_STATE_AA32, > + .cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, > .type = ARM_CP_ALIAS, > .access = PL1_R, .accessfn = access_tda, > .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), }, Applied to target-arm.next, thanks. -- PMM