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From: Peter Maydell <peter.maydell@linaro.org>
To: Greg Bellows <greg.bellows@linaro.org>
Cc: "Alex Bennée" <alex.bennee@linaro.org>,
	"QEMU Developers" <qemu-devel@nongnu.org>,
	"Christoffer Dall" <christoffer.dall@linaro.org>
Subject: Re: [Qemu-devel] [PATCH v3 1/4] target-arm: Add CPU property to disable AArch64
Date: Tue, 3 Feb 2015 19:14:08 +0000	[thread overview]
Message-ID: <CAFEAcA9EcObstXD1fSMoshs++P_rj7dBcK3aNekWyyH=zhthhQ@mail.gmail.com> (raw)
In-Reply-To: <1422403117-16921-2-git-send-email-greg.bellows@linaro.org>

On 27 January 2015 at 23:58, Greg Bellows <greg.bellows@linaro.org> wrote:
> Adds registration and get/set functions for enabling/disabling the AArch64
> execution state on AArch64 CPUs.  By default AArch64 execution state is enabled
> on AArch64 CPUs, setting the property to off, will disable the execution state.
> The below QEMU invocation would have AArch64 execution state disabled.
>
>     $ ./qemu-system-aarch64 -machine virt -cpu cortex-a57,aarch64=off
>
> Also adds stripping of features from CPU model string in acquiring the ARM CPU
> by name.
>
> Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
>
> ---
>
> v1 -> v2
> - Scrap the custom CPU feature parsing in favor of using the default CPU
>   parsing.
> - Add registration of CPU AArch64 property to disable/enable the AArch64
>   feature.
> ---
>  target-arm/cpu.c   |  6 +++++-
>  target-arm/cpu64.c | 29 +++++++++++++++++++++++++++++
>  2 files changed, 34 insertions(+), 1 deletion(-)
>
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index 285947f..29ed691 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -514,13 +514,17 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
>  {
>      ObjectClass *oc;
>      char *typename;
> +    char *cpuname;
>
>      if (!cpu_model) {
>          return NULL;
>      }
>
> -    typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
> +    cpuname = g_strdup(cpu_model);
> +    cpuname = strtok(cpuname, ",");

strtok isn't thread safe. Let's just use g_strsplit like we did
in virt.c and then we don't have to worry about whether or not
multiple threads could ever end up here at the same time.

> +    typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname);
>      oc = object_class_by_name(typename);
> +    g_free(cpuname);
>      g_free(typename);
>      if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
>          object_class_is_abstract(oc)) {
> diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
> index bb778b3..5a59280 100644
> --- a/target-arm/cpu64.c
> +++ b/target-arm/cpu64.c
> @@ -32,6 +32,11 @@ static inline void set_feature(CPUARMState *env, int feature)
>      env->features |= 1ULL << feature;
>  }
>
> +static inline void unset_feature(CPUARMState *env, int feature)
> +{
> +    env->features &= ~(1ULL << feature);
> +}
> +
>  #ifndef CONFIG_USER_ONLY
>  static uint64_t a57_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
>  {
> @@ -170,8 +175,32 @@ static const ARMCPUInfo aarch64_cpus[] = {
>      { .name = NULL }
>  };
>
> +static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
> +{
> +    ARMCPU *cpu = ARM_CPU(obj);
> +
> +    return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
> +}
> +
> +static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
> +{
> +    ARMCPU *cpu = ARM_CPU(obj);
> +
> +    if (value == false) {
> +        unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
> +    } else {
> +        set_feature(&cpu->env, ARM_FEATURE_AARCH64);
> +    }
> +}
> +
>  static void aarch64_cpu_initfn(Object *obj)
>  {
> +    object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64,
> +                             aarch64_cpu_set_aarch64, NULL);
> +    object_property_set_description(obj, "aarch64",
> +                                    "Set on/off to enable/disable aarch64 "
> +                                    "execution state ",
> +                                    NULL);
>  }

This all looks OK code-wise. Still need to think about whether we
can manage to end up with a nicer interface to the user than
cpuname,-aarch64, though.

-- PMM

  reply	other threads:[~2015-02-03 19:14 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-01-27 23:58 [Qemu-devel] [PATCH v3 0/4] target-arm: ARM64: Adding EL1 AARCH32 guest support Greg Bellows
2015-01-27 23:58 ` [Qemu-devel] [PATCH v3 1/4] target-arm: Add CPU property to disable AArch64 Greg Bellows
2015-02-03 19:14   ` Peter Maydell [this message]
2015-02-03 21:15     ` Peter Maydell
2015-02-03 21:21       ` Christoffer Dall
2015-02-03 21:45         ` Greg Bellows
2015-02-03 21:46     ` Greg Bellows
2015-01-27 23:58 ` [Qemu-devel] [PATCH v3 2/4] target-arm: Add feature parsing to virt Greg Bellows
2015-02-03 19:10   ` Peter Maydell
2015-01-27 23:58 ` [Qemu-devel] [PATCH v3 3/4] target-arm: Add 32/64-bit register sync Greg Bellows
2015-02-03 18:54   ` Peter Maydell
2015-02-04 18:44     ` Greg Bellows
2015-02-04 23:37     ` Greg Bellows
2015-02-05  8:28       ` Peter Maydell
2015-01-27 23:58 ` [Qemu-devel] [PATCH v3 4/4] target-arm: Add AArch32 guest support to KVM64 Greg Bellows
2015-02-03 19:04   ` Peter Maydell
2015-01-29 10:13 ` [Qemu-devel] [PATCH v3 0/4] target-arm: ARM64: Adding EL1 AARCH32 guest support Christoffer Dall

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