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From: Peter Maydell <peter.maydell@linaro.org>
To: Richard Henderson <rth@twiddle.net>
Cc: "walt@tilera.com" <walt@tilera.com>,
	Chris Metcalf <cmetcalf@ezchip.com>,
	QEMU Developers <qemu-devel@nongnu.org>,
	Chen Gang <xili_gchen_5257@hotmail.com>
Subject: Re: [Qemu-devel] [PATCH v14 22/33] target-tilegx: Implement system and memory management instructions
Date: Sat, 29 Aug 2015 22:21:46 +0100	[thread overview]
Message-ID: <CAFEAcA9M+JVOBrwnP3Hf46-+J1ZQNHq7y5z9y9rMSt3-Dhv9_g@mail.gmail.com> (raw)
In-Reply-To: <1440433079-14458-23-git-send-email-rth@twiddle.net>

On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> Most of which are either nops or exceptions.
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  target-tilegx/translate.c | 94 ++++++++++++++++++++++++++++++++++-------------
>  1 file changed, 68 insertions(+), 26 deletions(-)
>
> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
> index ea68902..5bdc8be 100644
> --- a/target-tilegx/translate.c
> +++ b/target-tilegx/translate.c
> @@ -241,27 +241,82 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
>      TCGv tdest, tsrca;
>      const char *mnemonic;
>      TCGMemOp memop;
> +    TileExcp ret = TILEGX_EXCP_NONE;
>
> -    /* Eliminate nops and jumps before doing anything else.  */
> +    /* Eliminate instructions with no output before doing anything else.  */
>      switch (opext) {
>      case OE_RR_Y0(NOP):
>      case OE_RR_Y1(NOP):
>      case OE_RR_X0(NOP):
>      case OE_RR_X1(NOP):
>          mnemonic = "nop";
> -        goto do_nop;
> +        goto done0;
>      case OE_RR_Y0(FNOP):
>      case OE_RR_Y1(FNOP):
>      case OE_RR_X0(FNOP):
>      case OE_RR_X1(FNOP):
>          mnemonic = "fnop";
> -    do_nop:
> -        if (srca || dest) {
> -            return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> +        goto done0;
> +    case OE_RR_X1(DRAIN):
> +        mnemonic = "drain";
> +        goto done0;
> +    case OE_RR_X1(FLUSHWB):
> +        mnemonic = "flushwb";
> +        goto done0;
> +    case OE_RR_X1(ILL):
> +    case OE_RR_Y1(ILL):
> +        ret = TILEGX_EXCP_OPCODE_UNKNOWN;
> +        mnemonic = (dest == 0x1c && srca == 0x25 ? "bpt" : "ill");
> +        goto done0;
> +    case OE_RR_X1(MF):
> +        mnemonic = "mf";
> +        goto done0;
> +    case OE_RR_X1(NAP):
> +        /* ??? This should yield, especially in system mode.  */
> +        mnemonic = "nap";
> +        goto done0;
> +    case OE_RR_X1(SWINT0):
> +        ret = TILEGX_EXCP_OPCODE_UNKNOWN;
> +        mnemonic = "swint0";
> +        goto done0;
> +    case OE_RR_X1(SWINT1):
> +        ret = TILEGX_EXCP_SYSCALL;
> +        mnemonic = "swint1";
> +        goto done0;
> +    case OE_RR_X1(SWINT2):
> +        ret = TILEGX_EXCP_OPCODE_UNKNOWN;
> +        mnemonic = "swint2";
> +        goto done0;
> +    case OE_RR_X1(SWINT3):
> +        ret = TILEGX_EXCP_OPCODE_UNKNOWN;
> +        mnemonic = "swint3";
> +        goto done0;
> +    done0:

goto to immediately following label ?

> +        if ((srca || dest) && ret == TILEGX_EXCP_NONE) {
> +            ret = TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
>          }
>          qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
> -        return TILEGX_EXCP_NONE;
> +        return ret;
>
> +    case OE_RR_X1(DTLBPR):
> +        ret = TILEGX_EXCP_OPCODE_UNKNOWN;
> +        mnemonic = "dtlbpr";
> +        goto done1;
> +    case OE_RR_X1(FINV):
> +        mnemonic = "finv";
> +        goto done1;
> +    case OE_RR_X1(FLUSH):
> +        mnemonic = "flush";
> +        goto done1;
> +    case OE_RR_X1(ICOH):
> +        mnemonic = "icoh";
> +        goto done1;
> +    case OE_RR_X1(INV):
> +        mnemonic = "inv";
> +        goto done1;
> +    case OE_RR_X1(WH64):
> +        mnemonic = "wh64";
> +        goto done1;
>      case OE_RR_X1(JRP):
>      case OE_RR_Y1(JRP):
>          mnemonic = "jrp";
> @@ -284,8 +339,12 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
>          dc->jmp.cond = TCG_COND_ALWAYS;
>          dc->jmp.dest = tcg_temp_new();
>          tcg_gen_andi_tl(dc->jmp.dest, load_gr(dc, srca), ~7);

Should this really fall through into the added check ?

> +    done1:
> +        if (dest && ret == TILEGX_EXCP_NONE) {
> +            ret = TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> +        }
>          qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s", mnemonic, reg_names[srca]);
> -        return TILEGX_EXCP_NONE;
> +        return ret;
>      }
>
>      tdest = dest_gr(dc, dest);
> @@ -302,17 +361,8 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
>          gen_helper_cnttz(tdest, tsrca);
>          mnemonic = "cnttz";
>          break;
> -    case OE_RR_X1(DRAIN):
> -    case OE_RR_X1(DTLBPR):
> -    case OE_RR_X1(FINV):
> -    case OE_RR_X1(FLUSHWB):
> -    case OE_RR_X1(FLUSH):
>      case OE_RR_X0(FSINGLE_PACK1):
>      case OE_RR_Y0(FSINGLE_PACK1):
> -    case OE_RR_X1(ICOH):
> -    case OE_RR_X1(ILL):
> -    case OE_RR_Y1(ILL):
> -    case OE_RR_X1(INV):
>      case OE_RR_X1(IRET):
>          return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
>      case OE_RR_X1(LD1S):
> @@ -381,14 +431,11 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
>      case OE_RR_X1(LNK):
>      case OE_RR_Y1(LNK):
>          if (srca) {
> -            return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> +            ret = TILEGX_EXCP_OPCODE_UNIMPLEMENTED;

This code change seems unrelated to the rest of the patch?
Also we'll end up printing the disassembly as "lnk" rather
than whatever we should print for undefined instructions.

>          }
>          tcg_gen_movi_tl(tdest, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
>          mnemonic = "lnk";
>          break;
> -    case OE_RR_X1(MF):
> -    case OE_RR_X1(NAP):
> -        return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
>      case OE_RR_X0(PCNT):
>      case OE_RR_Y0(PCNT):
>          gen_helper_pcnt(tdest, tsrca);
> @@ -404,10 +451,6 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
>          tcg_gen_bswap64_tl(tdest, tsrca);
>          mnemonic = "revbytes";
>          break;
> -    case OE_RR_X1(SWINT0):
> -    case OE_RR_X1(SWINT1):
> -    case OE_RR_X1(SWINT2):
> -    case OE_RR_X1(SWINT3):
>      case OE_RR_X0(TBLIDXB0):
>      case OE_RR_Y0(TBLIDXB0):
>      case OE_RR_X0(TBLIDXB1):
> @@ -416,14 +459,13 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
>      case OE_RR_Y0(TBLIDXB2):
>      case OE_RR_X0(TBLIDXB3):
>      case OE_RR_Y0(TBLIDXB3):
> -    case OE_RR_X1(WH64):
>      default:
>          return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
>      }
>
>      qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
>                    reg_names[dest], reg_names[srca]);
> -    return TILEGX_EXCP_NONE;
> +    return ret;
>  }
>
>  static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,

thanks
-- PMM

  reply	other threads:[~2015-08-29 21:22 UTC|newest]

Thread overview: 80+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 01/33] linux-user: tilegx: Firstly add architecture related features Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 02/33] linux-user: Support tilegx architecture in linux-user Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 03/33] linux-user: Conditionalize syscalls which are not defined in tilegx Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 04/33] target-tilegx: Add opcode basic implementation from Tilera Corporation Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 05/33] target-tilegx: Modify opcode_tilegx.h to fit QEMU usage Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 06/33] target-tilegx: Modify _SPECIAL_ opcodes Richard Henderson
2015-08-29 14:29   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 07/33] target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1 Richard Henderson
2015-08-24 16:29   ` Peter Maydell
2015-08-24 16:43     ` Richard Henderson
2015-08-26 17:11   ` Chris Metcalf
2015-08-29 14:30   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 08/33] target-tilegx: Add special register information from Tilera Corporation Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 09/33] target-tilegx: Add cpu basic features for linux-user Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 10/33] target-tilegx: Add several helpers for instructions translation Richard Henderson
2015-08-29 14:37   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 11/33] target-tilegx: Framework for decoding bundles Richard Henderson
2015-08-29 14:50   ` Peter Maydell
     [not found]     ` <55E24808.5000302@hotmail.com>
2015-08-30  0:01       ` Chen Gang
2015-08-29 21:08   ` Peter Maydell
2015-09-01  1:58     ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 12/33] target-tilegx: Generate SEGV properly Richard Henderson
2015-08-29 14:51   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 14/33] target-tilegx: Handle simple logical operations Richard Henderson
2015-08-29 14:58   ` Peter Maydell
2015-09-01  2:10     ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 15/33] target-tilegx: Handle arithmetic instructions Richard Henderson
2015-08-29 15:03   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 16/33] target-tilegx: Handle most bit manipulation instructions Richard Henderson
2015-08-29 15:26   ` Peter Maydell
2015-09-01  2:26     ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 17/33] target-tilegx: Handle basic load and store instructions Richard Henderson
2015-08-29 20:45   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 18/33] target-tilegx: Handle post-increment " Richard Henderson
2015-08-29 20:52   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 19/33] target-tilegx: Handle unconditional jump instructions Richard Henderson
2015-08-29 21:00   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 20/33] target-tilegx: Handle conditional branch instructions Richard Henderson
2015-08-29 21:08   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 21/33] target-tilegx: Handle comparison instructions Richard Henderson
2015-08-29 21:12   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 22/33] target-tilegx: Implement system and memory management instructions Richard Henderson
2015-08-29 21:21   ` Peter Maydell [this message]
2015-09-01  5:16     ` Richard Henderson
2015-09-01  8:23       ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 23/33] target-tilegx: Handle bitfield instructions Richard Henderson
2015-08-30 13:31   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 24/33] target-tilegx: Handle shift instructions Richard Henderson
2015-08-30 13:38   ` Peter Maydell
2015-09-01  5:37     ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 25/33] target-tilegx: Handle conditional move instructions Richard Henderson
2015-08-30 13:40   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 26/33] target-tilegx: Handle scalar multiply instructions Richard Henderson
2015-08-30 13:46   ` Peter Maydell
2015-09-01  5:42     ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 27/33] target-tilegx: Handle mask instructions Richard Henderson
2015-08-30 13:52   ` Peter Maydell
2015-09-01  5:43     ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 28/33] target-tilegx: Handle v1cmpeq, v1cmpne Richard Henderson
2015-08-30 15:11   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 29/33] target-tilegx: Handle mtspr, mfspr Richard Henderson
2015-08-30 15:18   ` Peter Maydell
2015-09-01  5:48     ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic instructions Richard Henderson
2015-08-25  4:15   ` Richard Henderson
     [not found]     ` <55DC69B0.1040000@hotmail.com>
2015-08-25 13:11       ` Chen Gang
2015-08-25 13:12         ` Chen Gang
2015-08-25 14:28           ` Richard Henderson
     [not found]             ` <55DCE21F.9000103@hotmail.com>
2015-08-25 21:45               ` Chen Gang
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 31/33] target-tilegx: Handle v4int_l/h Richard Henderson
2015-08-30 15:20   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 32/33] target-tilegx: Handle v1shli, v1shrui Richard Henderson
2015-08-30 15:23   ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 33/33] target-tilegx: Handle v1shl, v1shru, v1shrs Richard Henderson
2015-08-30 15:28   ` Peter Maydell
     [not found] ` <55DB96D7.9000105@hotmail.com>
2015-08-24 22:12   ` [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Chen Gang
     [not found]     ` <55E1B1AF.3040407@hotmail.com>
2015-08-29 13:19       ` Chen Gang
     [not found]         ` <55E2822E.4000805@hotmail.com>
2015-08-30  4:09           ` Chen Gang
2015-09-10 15:29             ` Chen Gang

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