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Date: Thu, 24 Nov 2011 19:37:16 +0000
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From: Peter Maydell <peter.maydell@linaro.org>
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Subject: Re: [Qemu-devel] [PATCH V2 3/4] imx.31 and KZM board support:
	interrupt controller
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To: Peter Chubb <peter.chubb@nicta.com.au>
Cc: =?UTF-8?Q?Andreas_F=C3=A4rber?= <andreas.faerber@web.de>, qemu-devel@nongnu.org

On 22 November 2011 04:34, Peter Chubb <peter.chubb@nicta.com.au> wrote:
> Implement the FreeSCALE i.MX31 advanced vectored interrupt controller, at=
 least
> to the extent it is used by Linux 3.0.x
>
> Signed-off-by: Hans Jang <hsjang@ok-labs.com>
> Signed-off-by: Adam Clench <adamc@ok-labs.com>
> Signed-off-by: Peter Chubb <peter.chubb@nicta.com.au>
> ---
> =C2=A0hw/imx_avic.c | =C2=A0363 +++++++++++++++++++++++++++++++++++++++++=
+++++++++++++++++
> =C2=A01 file changed, 363 insertions(+)
> =C2=A0create mode 100644 hw/imx_avic.c
>
> Index: qemu-working/hw/imx_avic.c
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> --- /dev/null =C2=A0 1970-01-01 00:00:00.000000000 +0000
> +++ qemu-working/hw/imx_avic.c =C2=A02011-11-22 14:47:10.706040936 +1100
> @@ -0,0 +1,363 @@
> +/*
> + * IMX31 Vectored Interrupt Controller
> + *
> + * Note this is NOT the PL192 provided by ARM, but
> + * a custom implementation by FreeScale.
> + *
> + * Copyright (c) 2008 OKL
> + * Written by Hans
> + *
> + * This code is licenced under the GPL version 2 or later.
> + *
> + * TODO: implement vectors and priorities.
> + */
> +
> +#include "hw.h"
> +#include "sysbus.h"
> +#include <string.h> /* ffsll */

ffsll is a glibc extension. Use ctz64() from host-utils.h
instead (but check that the edge case of no bits set is
handled the way you need, the semantics aren't identical.)

> +
> +#define DEBUG_INT 1
> +#undef DEBUG_INT /* comment out for debugging */
> +
> +#ifdef DEBUG_INT
> +#define DPRINTF(fmt, args...) \
> +do { printf("imx_int: " fmt , ##args); } while (0)
> +#else
> +#define DPRINTF(fmt, args...) do {} while (0)
> +#endif
> +
> +/*
> + * Print a message at most ten times.
> + */
> +#define scream(fmt, args...) \
> + =C2=A0 =C2=A0do { \
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0static int printable =3D 10;\
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0if (printable--) { \
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0fprintf(stderr, fmt, ##args); =
\
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0} \
> + =C2=A0 =C2=A0} while (0)
> +
> +
> +#define IMX_INT_NUM_IRQS 64
> +
> +/* Interrupt Control Bits */
> +#define ABFLAG (1<<25)
> +#define ABFEN (1<<24)
> +#define NIDIS (1<<22) /* Normal Interrupt disable */
> +#define FIDIS (1<<21) /* Fast interrupt disable */
> +#define NIAD =C2=A0(1<<20) /* Normal Interrupt Arbiter Rise ARM level */
> +#define FIAD =C2=A0(1<<19) /* Fast Interrupt Arbiter Rise ARM level */
> +#define NM =C2=A0 =C2=A0(1<<18) /* Normal interrupt mode */
> +
> +
> +#define PRIO_PER_WORD (sizeof (uint32_t) * 8 / 4)
> +#define PRIO_WORDS (IMX_INT_NUM_IRQS/PRIO_PER_WORD)
> +
> +typedef struct {
> + =C2=A0 =C2=A0SysBusDevice busdev;
> + =C2=A0 =C2=A0MemoryRegion iomem;
> + =C2=A0 =C2=A0uint64_t pending;
> + =C2=A0 =C2=A0uint64_t enabled;
> + =C2=A0 =C2=A0uint64_t is_fiq;
> + =C2=A0 =C2=A0uint32_t intcntl;
> + =C2=A0 =C2=A0uint32_t intmask;
> + =C2=A0 =C2=A0qemu_irq irq;
> + =C2=A0 =C2=A0qemu_irq fiq;
> + =C2=A0 =C2=A0uint32_t prio[PRIO_WORDS]; /* Priorities are 4-bits each *=
/
> +} imx_int_state;
> +
> +static const VMStateDescription vmstate_imx_avic =3D {
> + =C2=A0 =C2=A0.name =3D "imx-avic",
> + =C2=A0 =C2=A0.version_id =3D 1,
> + =C2=A0 =C2=A0.minimum_version_id =3D 1,
> + =C2=A0 =C2=A0.minimum_version_id_old =3D 1,
> + =C2=A0 =C2=A0.fields =3D (VMStateField []) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT64(pending, imx_int_state),
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT64(enabled, imx_int_state),
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT64(is_fiq, imx_int_state),
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32(intcntl, imx_int_state),
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32(intmask, imx_int_state),
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32_ARRAY(prio, imx_int_state, PR=
IO_WORDS),
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_END_OF_LIST()
> + =C2=A0 =C2=A0},
> +};
> +
> +
> +
> +static inline int imx_int_prio(imx_int_state *s, int irq)
> +{
> + =C2=A0 =C2=A0uint32_t word =3D irq / PRIO_PER_WORD;
> + =C2=A0 =C2=A0uint32_t part =3D 4 * (irq % PRIO_PER_WORD);
> + =C2=A0 =C2=A0return 0xf & (s->prio[word] >> part);
> +}
> +
> +static inline void imx_int_set_prio(imx_int_state *s, int irq, int prio)
> +{
> + =C2=A0 =C2=A0uint32_t word =3D irq / PRIO_PER_WORD;
> + =C2=A0 =C2=A0uint32_t part =3D 4 * (irq % PRIO_PER_WORD);
> + =C2=A0 =C2=A0uint32_t mask =3D ~(0xf << part);
> + =C2=A0 =C2=A0s->prio[word] &=3D mask;
> + =C2=A0 =C2=A0s->prio[word] |=3D prio << part;
> +}

We don't seem to ever call this function?

> +/* Update interrupts. =C2=A0*/
> +static void imx_int_update(imx_int_state *s)
> +{
> + =C2=A0 =C2=A0int i;
> + =C2=A0 =C2=A0uint64_t new =3D s->pending;
> + =C2=A0 =C2=A0uint64_t flags;
> +
> + =C2=A0 =C2=A0flags =3D new & s->enabled & s->is_fiq;
> + =C2=A0 =C2=A0qemu_set_irq(s->fiq, !!flags);
> +
> + =C2=A0 =C2=A0flags =3D new & s->enabled & ~s->is_fiq;
> + =C2=A0 =C2=A0if (!flags || ((s->intmask & 0x1f) =3D=3D 0x1f)) {

This &0x1f is only needed because you're incorrectly allowing
the high bits of the register to get set (see below).

> + =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_set_irq(s->irq, !!flags);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return;
> + =C2=A0 =C2=A0}
> +
> + =C2=A0 =C2=A0/* Take interrupt if =C2=A0prio lower than the value of in=
tmask */

stray space.

> + =C2=A0 =C2=A0for (i =3D 0; i < IMX_INT_NUM_IRQS; i++) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0if (flags & (1UL << i)) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (imx_int_prio(s, i) > s->in=
tmask) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_set_irq(s->=
irq, 1);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0}
> + =C2=A0 =C2=A0}

Should we be deasserting the irq line if none of the pending
interrupts have sufficient priority?

> +
> +}
> +
> +static void imx_int_set_irq(void *opaque, int irq, int level)
> +{
> + =C2=A0 =C2=A0imx_int_state *s =3D (imx_int_state *)opaque;
> +
> + =C2=A0 =C2=A0if (level) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0s->pending |=3D (1ULL << irq);
> + =C2=A0 =C2=A0} else {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0s->pending &=3D ~(1ULL << irq);
> + =C2=A0 =C2=A0}
> +
> + =C2=A0 =C2=A0imx_int_update(s);
> +}
> +
> +
> +static uint64_t imx_int_read(void *opaque,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 target_phys_addr_t offset, unsigned size)
> +{
> + =C2=A0 =C2=A0imx_int_state *s =3D (imx_int_state *)opaque;
> +
> +
> + =C2=A0 =C2=A0DPRINTF("read(offset =3D 0x%x)\n", offset >> 2);
> + =C2=A0 =C2=A0switch (offset >> 2) {
> + =C2=A0 =C2=A0case 0: /* INTCNTL */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return s->intcntl;
> +
> + =C2=A0 =C2=A0case 1: /* Normal Interrupt Mask Register, NIMASK */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return s->intmask;
> +
> + =C2=A0 =C2=A0case 2: /* Interrupt Enable Number Register, INTENNUM */
> + =C2=A0 =C2=A0case 3: /* Interrupt Disable Number Register, INTDISNUM */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;
> +
> + =C2=A0 =C2=A0case 4: /* Interrupt Enabled Number Register High */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return s->enabled >> 32;
> +
> + =C2=A0 =C2=A0case 5: /* Interrupt Enabled Number Register Low */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return s->enabled & 0xffffffffULL;
> +
> + =C2=A0 =C2=A0case 6: /* Interrupt Type Register High */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return s->is_fiq >> 32;
> +
> + =C2=A0 =C2=A0case 7: /* Interrupt Type Register Low */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return s->is_fiq & 0xFFFFFFFFULL;
> +
> + =C2=A0 =C2=A0case 8: /* Normal Interrupt Priority Register 7 */
> + =C2=A0 =C2=A0case 9: /* Normal Interrupt Priority Register 6 */
> + =C2=A0 =C2=A0case 10:/* Normal Interrupt Priority Register 5 */
> + =C2=A0 =C2=A0case 11:/* Normal Interrupt Priority Register 4 */
> + =C2=A0 =C2=A0case 12:/* Normal Interrupt Priority Register 3 */
> + =C2=A0 =C2=A0case 13:/* Normal Interrupt Priority Register 2 */
> + =C2=A0 =C2=A0case 14:/* Normal Interrupt Priority Register 1 */
> + =C2=A0 =C2=A0case 15:/* Normal Interrupt Priority Register 0 */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return s->prio[15-(offset>>2)];
> +
> + =C2=A0 =C2=A0case 16: /* Normal interrupt vector and status register */
> + =C2=A0 =C2=A0{
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t flags =3D s->pending & s->enabled &=
 ~s->is_fiq;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0int i =3D ffsll(flags);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0if (i) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0imx_int_set_irq(opaque, i-1, 0=
);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return (i-1) << 16;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0}
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return 0xFFFFULL<<16;
> + =C2=A0 =C2=A0}
> + =C2=A0 =C2=A0case 17:/* Fast Interrupt vector and status register */
> + =C2=A0 =C2=A0{
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t flags =3D s->pending & s->enabled &=
 s->is_fiq;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0int i =3D ffsll(flags);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0if (i) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0imx_int_set_irq(opaque, i-1, 0=
);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return (i-1) << 16;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0}
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return 0xFFFF<<16;

Why ULL in the previous cases and not this one?

> + =C2=A0 =C2=A0}
> + =C2=A0 =C2=A0case 18:/* Interrupt source register high */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return s->pending >> 32;
> +
> + =C2=A0 =C2=A0case 19:/* Interrupt source register low */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return s->pending & 0xFFFFFFFFULL;
> +
> + =C2=A0 =C2=A0case 20:/* Interrupt Force Register high */
> + =C2=A0 =C2=A0case 21:/* Interrupt Force Register low */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;
> +
> + =C2=A0 =C2=A0case 22:/* Normal Interrupt Pending Register High */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return (s->pending & s->enabled & ~s->is_fiq=
) >> 32;
> +
> + =C2=A0 =C2=A0case 23:/* Normal Interrupt Pending Register Low */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return (s->pending & s->enabled & ~s->is_fiq=
) & 0xFFFFFFFFULL;
> +
> + =C2=A0 =C2=A0case 24: /* Fast Interrupt Pending Register High =C2=A0*/
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return (s->pending & s->enabled & s->is_fiq)=
 >> 32;
> +
> + =C2=A0 =C2=A0case 25: /* Fast Interrupt Pending Register Low =C2=A0*/
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return (s->pending & s->enabled & s->is_fiq)=
 & 0xFFFFFFFFULL;
> +
> + =C2=A0 =C2=A0case 0x40: =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* AVI=
C vector 0, use for WFI WAR */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return 0x4;
> +
> + =C2=A0 =C2=A0default:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0scream("imx_int_read: Bad offset 0x%x\n", (i=
nt)offset);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;
> + =C2=A0 =C2=A0}
> +}
> +
> +static void imx_int_write(void *opaque, target_phys_addr_t offset,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0uint64_t val, unsigned size)
> +{
> + =C2=A0 =C2=A0imx_int_state *s =3D (imx_int_state *)opaque;
> +
> + =C2=A0 =C2=A0/* Vector Registers not yet supported */
> + =C2=A0 =C2=A0if (offset >=3D 0x100 && offset <=3D 0x2fc) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0DPRINTF("imx_int_write to vector register %d=
\n",
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(offset - 0x100)=
>>2);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return;
> + =C2=A0 =C2=A0}
> +
> + =C2=A0 =C2=A0DPRINTF("imx_int_write(0x%x) =3D %x\n",
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(unsigned int)offset>>2, (unsi=
gned int)val);
> + =C2=A0 =C2=A0switch (offset >> 2) {
> + =C2=A0 =C2=A0case 0: /* Interrupt Control Register, INTCNTL */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0s->intcntl =3D val;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
> +
> + =C2=A0 =C2=A0case 1: /* Normal Interrupt Mask Register, NIMASK */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0s->intmask =3D val;

The manual I have documents this register as only having five
significant bits, with the upper bits all being reads-as-zero,
writes-ignored. This implements them as being read-write.
(Please check the other registers to see if they have similar bugs.)

> + =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
> +
> + =C2=A0 =C2=A0case 2: /* Interrupt Enable Number Register, INTENNUM */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0DPRINTF("enable(%d)\n", (int)val);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0s->enabled |=3D (1ULL << val);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
> +
> + =C2=A0 =C2=A0case 3: /* Interrupt Disable Number Register, INTDISNUM */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0s->enabled &=3D ~(1ULL << val);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0DPRINTF("disabled(%d)\n", (int)val);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
> +
> + =C2=A0 =C2=A0case 4: /* Interrupt Enable Number Register High */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0s->enabled =3D (s->enabled & 0xffffffffULL) =
| (val << 32);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
> +
> + =C2=A0 =C2=A0case 5: /* Interrupt Enable Number Register Low */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0s->enabled =3D (s->enabled & 0xffffffff00000=
000ULL) | val;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
> +
> + =C2=A0 =C2=A0case 6: /* Interrupt Type Register High */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0s->is_fiq =3D (s->is_fiq & 0xffffffffULL) | =
(val << 32);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
> +
> + =C2=A0 =C2=A0case 7: /* Interrupt Type Register Low */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0s->is_fiq =3D (s->is_fiq & 0xffffffff0000000=
0ULL) | val;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
> +
> + =C2=A0 =C2=A0case 8: /* Normal Interrupt Priority Register 7 */
> + =C2=A0 =C2=A0case 9: /* Normal Interrupt Priority Register 6 */
> + =C2=A0 =C2=A0case 10:/* Normal Interrupt Priority Register 5 */
> + =C2=A0 =C2=A0case 11:/* Normal Interrupt Priority Register 4 */
> + =C2=A0 =C2=A0case 12:/* Normal Interrupt Priority Register 3 */
> + =C2=A0 =C2=A0case 13:/* Normal Interrupt Priority Register 2 */
> + =C2=A0 =C2=A0case 14:/* Normal Interrupt Priority Register 1 */
> + =C2=A0 =C2=A0case 15:/* Normal Interrupt Priority Register 0 */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0s->prio[15-(offset>>2)] =3D val;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return;
> +
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Read-only registers, writes ignored */
> + =C2=A0 =C2=A0case 16:/* Normal Interrupt Vector and Status register */
> + =C2=A0 =C2=A0case 17:/* Fast Interrupt vector and status register */
> + =C2=A0 =C2=A0case 18:/* Interrupt source register high */
> + =C2=A0 =C2=A0case 19:/* Interrupt source register low */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return;
> +
> + =C2=A0 =C2=A0case 20:/* Interrupt Force Register high */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0s->pending =3D (s->pending & 0xffffffffULL) =
| (val << 32);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
> +
> + =C2=A0 =C2=A0case 21:/* Interrupt Force Register low */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0s->pending =3D (s->pending & 0xffffffff00000=
000ULL) | val;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
> +
> + =C2=A0 =C2=A0case 22:/* Normal Interrupt Pending Register High */
> + =C2=A0 =C2=A0case 23:/* Normal Interrupt Pending Register Low */
> + =C2=A0 =C2=A0case 24: /* Fast Interrupt Pending Register High =C2=A0*/
> + =C2=A0 =C2=A0case 25: /* Fast Interrupt Pending Register Low =C2=A0*/
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return;
> +
> + =C2=A0 =C2=A0default:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0scream("imx_int_write: Bad offset %x\n", (in=
t)offset);
> + =C2=A0 =C2=A0}
> + =C2=A0 =C2=A0imx_int_update(s);
> +}
> +
> +static const MemoryRegionOps imx_int_ops =3D {
> + =C2=A0 =C2=A0.read =3D imx_int_read,
> + =C2=A0 =C2=A0.write =3D imx_int_write,
> + =C2=A0 =C2=A0.endianness =3D DEVICE_NATIVE_ENDIAN,
> +};
> +
> +static void imx_int_reset(imx_int_state *s)
> +{
> + =C2=A0 =C2=A0s->intmask =3D 0x1f;
> + =C2=A0 =C2=A0s->enabled =3D 0;
> +}
> +
> +static int imx_int_init(SysBusDevice *dev)
> +{
> + =C2=A0 =C2=A0imx_int_state *s =3D FROM_SYSBUS(imx_int_state, dev);;
> +
> + =C2=A0 =C2=A0memory_region_init_io(&s->iomem, &imx_int_ops, s, "imx_int=
", 0x1000);
> + =C2=A0 =C2=A0sysbus_init_mmio_region(dev, &s->iomem);
> +
> + =C2=A0 =C2=A0qdev_init_gpio_in(&dev->qdev, imx_int_set_irq, IMX_INT_NUM=
_IRQS);
> + =C2=A0 =C2=A0sysbus_init_irq(dev, &s->irq);
> + =C2=A0 =C2=A0sysbus_init_irq(dev, &s->fiq);
> +
> + =C2=A0 =C2=A0imx_int_reset(s);
> +
> + =C2=A0 =C2=A0vmstate_register(&dev->qdev, -1, &vmstate_imx_avic, s);

Use a SysBusDeviceInfo struct and set .qdev.vmsd.

> + =C2=A0 =C2=A0return 0;
> +}
> +
> +static void imx_int_register_devices(void)
> +{
> + =C2=A0 =C2=A0SysBusDeviceInfo *info =3D g_malloc0(sizeof *info);
> + =C2=A0 =C2=A0info->qdev.name =3D "imx_int";
> + =C2=A0 =C2=A0info->qdev.desc =3D "i.MX Advanced Vector Interrupt Contro=
ller";
> + =C2=A0 =C2=A0info->qdev.size =3D sizeof(imx_int_state);
> + =C2=A0 =C2=A0info->init =3D imx_int_init;

No, this should be a static struct. See hw/pl190.c for a random example.

> + =C2=A0 =C2=A0sysbus_register_withprop(info);
> +}
> +
> +device_init(imx_int_register_devices)

-- PMM